公开(公告)号：US20110111583A1

公开(公告)日：2011-05-12

申请号：US13010563

申请日：2011-01-20

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。

公开(公告)号：US07911838B2

公开(公告)日：2011-03-22

申请号：US12622966

申请日：2009-11-20

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C11/5642 ,  G11C16/0483

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其它相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了解决这种耦合，特定存储器单元的读取过程将向相邻存储器单元提供补偿，以便减少相邻存储单元对特定存储单元具有的耦合效应。

公开(公告)号：US20110026353A1

公开(公告)日：2011-02-03

申请号：US12903067

申请日：2010-10-12

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C7/00

CPC分类号： G11C16/3418 ,  G11C16/3431

摘要： Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determining to perform a refresh of data stored in a first group of non-volatile storage elements in a device based on a condition of data in the first group, determining that a second group of non-volatile storage elements in the device should undergo a refresh procedure based on when the second group of non-volatile storage elements were last programmed relative to when the first group of non-volatile storage elements were last programmed, and performing the refresh procedure on the second group of non-volatile storage element.

摘要翻译： 公开了用于在非易失性存储设备中刷新数据的技术，其足以抵抗错误或损坏的数据位，但不会频繁地干扰存储器访问或者对存储器单元造成过度的应力。 一个实施例包括确定基于第一组中的数据的条件来执行存储在设备中的第一组非易失性存储元件中的数据的刷新，确定设备中的第二组非易失性存储元件应该 基于当第二组非易失性存储元件被最后编程为相对于第一组非易失性存储元件最后被编程的时间的时间来执行刷新过程，并且对第二组非易失性存储元件执行刷新过程 。

公开(公告)号：US07851851B2

公开(公告)日：2010-12-14

申请号：US11691939

申请日：2007-03-27

申请人： Nima Mokhlesi ,  Roy Scheuerlein

发明人： Nima Mokhlesi ,  Roy Scheuerlein

IPC分类号： H01L29/792

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926

摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.

摘要翻译： 单片三维NAND串包括位于第二存储单元上的第一存储单元。 外部在第二存储单元的半导体有源区上形成第一存储单元的半导体有源区，使得在第一存储单元的半导体有源区和第二存储单元的半导体有源区之间存在限定的边界。

公开(公告)号：US07808831B2

公开(公告)日：2010-10-05

申请号：US12165302

申请日：2008-06-30

申请人： Nima Mokhlesi ,  Klaus Schuegraf

发明人： Nima Mokhlesi ,  Klaus Schuegraf

IPC分类号： G11C16/06

CPC分类号： G11C11/5642 ,  G11C16/3418 ,  G11C16/3427 ,  G11C29/00

摘要： Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is randomly chosen and its storage elements are sensed to determine optimized read compare levels for reading the selected word line. Or, a refresh operation may be indicated for the entire block based on an error correction metric obtained in reading the storage elements of the chosen word line. This is useful especially when the selected word line is repeatedly selected for reading, exposing the other word lines to additional read disturb. In another aspect, when multiple data states are stored, one read compare level is obtained from sensing, e.g., from a threshold voltage distribution, and other read compare levels are derived from a formula.

摘要翻译： 非易失性存储器中的读取干扰减少。 在一个方面，当从主机接收到用于读取所选择的字线的读取命令时，随机选择未被选择用于读取的字线，并且感测其存储元件以确定用于读取所选字线的优化读取比较电平 。 或者，可以基于在读取所选字线的存储元件中获得的纠错度量，针对整个块指示刷新操作。 特别是当所选字线被重复选择用于读取时，这是有用的，将其它字线暴露于额外的读取干扰。 在另一方面，当存储多个数据状态时，通过例如来自阈值电压分布的感测获得一个读取比较电平，并且从公式导出其它读取的比较电平。

公开(公告)号：US07808038B2

公开(公告)日：2010-10-05

申请号：US11691858

申请日：2007-03-27

申请人： Nima Mokhlesi ,  Roy Scheuerlein

发明人： Nima Mokhlesi ,  Roy Scheuerlein

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11556 ,  H01L27/11568

摘要： A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. A semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar.

摘要翻译： 单片三维NAND串包括位于第二存储单元上的第一存储单元。 第一存储单元的半导体有源区是从上方观察时具有正方形或矩形截面的第一柱，第一柱是位于第二导电型半导体区之间的第一导电型半导体区。 第二存储单元的半导体有源区是当从上方观察时具有正方形或矩形横截面的第二柱，位于第一柱下方的第二柱，第二柱是位于第二导电型半导体 地区。 第一柱中的一个第二导电类型半导体区域接触第二柱中的一个第二导电类型半导体区域。

公开(公告)号：US20100202207A1

公开(公告)日：2010-08-12

申请号：US12767660

申请日：2010-04-26

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/04

CPC分类号： G11C7/02 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.

公开(公告)号：US07755132B2

公开(公告)日：2010-07-13

申请号：US11465025

申请日：2006-08-16

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： H01L29/788 ,  H01L21/8247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： In a nonvolatile memory using floating gates to store charge, individual floating gates are L-shaped. Orientations of L-shaped floating gates may alternate in the bit line direction and may also alternate in the word line direction. L-shaped floating gates are formed by etching conductive portions using etch masks of different patterns to obtain floating gates of different orientations.

摘要翻译： 在使用浮动门来存储电荷的非易失性存储器中，各个浮动门是L形的。 L形浮栅的方向可以在位线方向上交替，并且也可以在字线方向上交替。 通过使用不同图案的蚀刻掩模蚀刻导电部分来形成L形浮栅，以获得不同取向的浮动栅极。

公开(公告)号：US20100128525A1

公开(公告)日：2010-05-27

申请号：US12323413

申请日：2008-11-25

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C16/00 ,  G11C16/06 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for verifying that memory cells comply with a target threshold voltage that is negative. The technique can be used for an erase verify or a soft program verify. One or more erase pulses are applied to a group of non-volatile storage elements that are associated with bit lines and word lines. One or more non-negative compare voltages (e.g., zero volts) are applied to at least a portion of the word lines after applying the erase pulses. Conditions on the bit lines are sensed while holding differences between voltages on the bit lines substantially constant and while applying the one or more compare voltages. A determination is made whether the group is sufficiently erased based on the conditions. At least one additional erase pulse is applied to the group of non-volatile storage elements if the group of non-volatile storage elements are not sufficiently erased.

摘要翻译： 本文公开了用于验证存储器单元符合负的目标阈值电压的技术。 该技术可用于擦除验证或软件程序验证。 一个或多个擦除脉冲被施加到与位线和字线相关联的一组非易失性存储元件。 在施加擦除脉冲之后，将一个或多个非负比较电压（例如零伏）施加到字线的至少一部分。 感测位线上的条件，同时保持位线上的电压之间的差异基本上恒定，同时施加一个或多个比较电压。 根据条件确定组是否被充分擦除。 如果非易失性存储元件组不被充分擦除，则至少一个附加擦除脉冲被施加到非易失性存储元件组。

公开(公告)号：US07684247B2

公开(公告)日：2010-03-23

申请号：US11537548

申请日：2006-09-29

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C11/06

CPC分类号： G11C8/10 ,  G11C11/5642 ,  G11C16/3418

摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.

摘要翻译： 由于存储在相邻（或其他）电荷存储区域中的电荷的电场耦合，可能会发生由非易失性存储单元中的诸如浮动栅极之类的电荷存储区域存储的表观电荷的变化。 尽管不是排他地，但是在选择的存储单元之后对相邻存储单元进行编程的情况下，效果最明显。 为了考虑视在电荷的偏移，基于由其他字线的存储元件存储的电荷来读取所选字线的存储元件时，应用一个或多个补偿。 高效补偿技术由存储单元的反向读取块（或其部分）提供。 通过以相反的编程方向读取，在读取所选单元格期间应用（或选择结果）所需的信息在相邻字线的实际读取操作期间被确定，而不是专用于读取操作来确定 信息。