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公开(公告)号:US20200045329A1
公开(公告)日:2020-02-06
申请号:US16597356
申请日:2019-10-09
Inventor: Takashi HASHIMOTO , Takahiro NISHI , Tadamasa TOMA , Kiyofumi ABE , Ryuichi KANOH
IPC: H04N19/513 , H04N19/176 , H04N19/105
Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.
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公开(公告)号:US20200014925A1
公开(公告)日:2020-01-09
申请号:US16574728
申请日:2019-09-18
Inventor: Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Takahiro NISHI , Ryuichi KANOH , Tadamasa TOMA
IPC: H04N19/122 , H04N19/176 , H04N19/103 , H04N19/513
Abstract: An encoding apparatus includes: a circuit; and a memory. The circuit, using the memory: writes a first parameter that specifies an arrangement order for a plurality of parameters which includes a second parameter, into a header; writes a second parameter for a block into a bitstream according to the arrangement order wherein the second parameter, when positioned earlier in the arrangement order than later in the arrangement order, is written with less bits; and performs encoding operation for a block using the second parameter.
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73.
公开(公告)号:US20190387286A1
公开(公告)日:2019-12-19
申请号:US16558466
申请日:2019-09-03
Inventor: Noritaka IGUCHI , Tadamasa TOMA , Hisaya KATOU
IPC: H04N21/643 , H04N21/43 , H04L7/00 , H04N21/236 , H04N21/2381 , H04N21/242 , H04N21/262 , H04N21/438 , H04N21/61
Abstract: A transmission method includes generating one or more frames for content transfer using IP (Internet Protocol) packets, and transmitting the one or more generated frames by broadcast. Each of the one or more frames contains a plurality of second transfer units, each of the plurality of second transfer units contains one or more first transfer units, and each of the one or more first transfer units contains at least one of the IP packets. An object IP packet of the IP packets which is stored in a first transfer unit positioned at a head in the one or more frames contains reference clock information that indicates time for reproduction of the content in data structure different from data structure of an MMT (MPEG Media Transport) packet, and header compression processing on the object IP packet is omitted.
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公开(公告)号:US20190335207A1
公开(公告)日:2019-10-31
申请号:US16395317
申请日:2019-04-26
Inventor: Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH
IPC: H04N19/80 , H04N19/563
Abstract: An encoder is an encoder which encodes a video, and includes: circuitry; and memory. The circuitry, using the memory, derives a motion vector of a current block included in a current picture, by referring to a reference picture different from the current picture; when a reference region indicated by the motion vector includes a region outside a boundary of the reference picture, performs padding for generating a plurality of pixels outside the boundary in the reference region, using one of a plurality of pixels inside the boundary of the reference picture, to generate the plurality of pixels outside the boundary; performs smoothing on the plurality of pixels outside the boundary; and generates a prediction image, using the plurality of pixels outside the boundary on which the smoothing has been performed.
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公开(公告)号:US20190313094A1
公开(公告)日:2019-10-10
申请号:US16450066
申请日:2019-06-24
Inventor: Ryuichi KANOH , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/117 , H04N19/159 , H04N19/136 , H04N19/176 , H04N19/61 , H04N19/182 , H04N19/82
Abstract: An encoder includes processing circuitry; and a memory coupled to the processing circuitry. Using the memory, the processing circuitry is configured to: change values of pixels in a first block and a second block to filter the boundary between the first block and the second block such that change amounts of the respective values are smaller than respective thresholds, the pixels being arranged along a line across the boundary; and encode a third block. The pixels in the first block include a first pixel located at a first position, and the pixels in the second block include a second pixel located at a second position corresponding to the first position with respect to the boundary. The thresholds include a first threshold and a second threshold corresponding to the first pixel and the second pixel, respectively. The first threshold is different from the second threshold.
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公开(公告)号:US20190273938A1
公开(公告)日:2019-09-05
申请号:US16291289
申请日:2019-03-04
Inventor: Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/52 , H04N19/176 , H04N19/70 , H04N19/44
Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: calculates at least one difference value between a plurality of pixels in a first block of a current image; calculates a denominator value used for a second block, using the difference value, the denominator value being used for a plurality of sub-blocks of the first block, the second block being one of the plurality of sub-blocks; determines a shift value, using the denominator value; calculates a first value and a second value, using at least a shift operation with the shift value; determines a prediction sample for the second block, using at least the first value and the second value; and encodes the second block, using at least the prediction sample.
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公开(公告)号:US20190273931A1
公开(公告)日:2019-09-05
申请号:US16417514
申请日:2019-05-20
Inventor: Chong Soon LIM , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Ru Ling LIAO , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/196 , H04N19/119 , H04N19/159 , H04N19/176
Abstract: An image encoder/decoder includes circuitry and a memory coupled to the circuitry. When a parameter has a first value, the circuitry splits a block of a picture into sub blocks having a first set of geometries. When the parameter has a value other than the first value, the circuitry splits the block of the picture into sub blocks having a second set of geometries, the second set of geometries being different from the first set of geometries. The circuitry encodes/decodes the sub blocks of the block.
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公开(公告)号:US20190273921A1
公开(公告)日:2019-09-05
申请号:US16287252
申请日:2019-02-27
Inventor: Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/119 , H04N19/46 , H04N19/107 , H04N19/176
Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: writes, into a bitstream, one or more parameters including a first parameter indicating that a first partition of an image is to be split into a plurality of partitions including at least a second partition which is a non-rectangular partition; splits the first partition, based on the first parameter; and encodes at least the second partition.
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公开(公告)号:US20190191167A1
公开(公告)日:2019-06-20
申请号:US16222104
申请日:2018-12-17
Inventor: Virginie DRUGEON , Tadamasa TOMA , Takahiro NISHI , Kiyofumi ABE , Ryuichi KANOH
IPC: H04N19/132 , H04N19/159 , H04N19/117 , H04N19/196 , H04N19/182
CPC classification number: H04N19/132 , H04N19/117 , H04N19/159 , H04N19/182 , H04N19/198
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs: deriving a plurality of reference samples positioned on a first line, for intra prediction; and generating a prediction image using the plurality of reference samples. The deriving includes interpolating a value on a second line perpendicular to the first line using values of encoded pixels on the second line to generate an interpolated value, and deriving one of the plurality of reference samples by projecting the interpolated value onto the first line.
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80.
公开(公告)号:US20190189006A1
公开(公告)日:2019-06-20
申请号:US16283200
申请日:2019-02-22
Inventor: Tadamasa TOMA , Takahiro NISHI , Toshiyasu SUGIO , Toru MATSUNOBU , Satoshi YOSHIKAWA , Tatsuya KOYAMA
IPC: G08G1/0968 , G01C21/36 , G01C21/32 , B60W30/182 , B60W50/00 , B60W50/10 , B60W50/14
CPC classification number: G08G1/0968 , B60W30/182 , B60W50/0097 , B60W50/10 , B60W50/14 , B60W2050/146 , G01C21/28 , G01C21/32 , G01C21/3655 , G01C21/367 , G05D1/02 , G08G1/09
Abstract: A three-dimensional information processing method includes: obtaining, via a communication channel, map data that includes first three-dimensional position information; generating second three-dimensional position information from information detected by a sensor; judging whether one of the first three-dimensional position information and the second three-dimensional position information is abnormal by performing, on one of the first three-dimensional position information and the second three-dimensional position information, a process of judging whether an abnormality is present; determining a coping operation to cope with the abnormality when one of the first three-dimensional position information and the second three-dimensional position information is judged to be abnormal; and executing a control that is required to perform the coping operation.
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