公开(公告)号：US20070101087A1

公开(公告)日：2007-05-03

申请号：US11264059

申请日：2005-10-31

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G06F13/00

CPC分类号： G06F13/4256

摘要： A memory module is configured to be arranged in a series configuration of memory modules. The memory module includes a clock synthesizer unit configured to regenerating an input clock signal of the memory module and to produce a regenerated clock signal. A first receiver is configured to receive a command and write data signal from a memory controller or from another memory module located upstream in the series configuration. A first transmitter is configured to transmit a read data signal from the memory module to the memory controller or to a previous memory module of the series configuration and to synchronize the read data signal transmitted from the memory module to the regenerated clock signal of the memory module. A second receiver is configured to receive the read data signal from a next memory module of the series configuration. A second transmitter is configured to transmit the command and write data signal to other memory modules located downstream in the series configuration and to synchronize the command and write data signal transmitted from the memory module to the regenerated clock signal of the memory module.

摘要翻译： 存储器模块被配置为以存储器模块的串联配置布置。 存储器模块包括时钟合成器单元，其被配置为再生存储器模块的输入时钟信号并产生再生的时钟信号。 第一接收器被配置为从存储器控制器或位于串联配置上游的另一个存储器模块接收命令和写入数据信号。 第一发射器被配置为将读取数据信号从存储器模块传输到存储器控制器或串联配置的先前存储器模块，并且将从存储器模块发送的读取数据信号同步到存储器模块的再生时钟信号 。 第二接收器被配置为从串联配置的下一个存储器模块接收读取数据信号。 第二发送器被配置为将命令和数据信号发送到位于串联配置下游的其他存储器模块，并且将从存储器模块发送的命令和写入数据信号同步到存储器模块的再生时钟信号。

公开(公告)号：US20070071156A1

公开(公告)日：2007-03-29

申请号：US11238331

申请日：2005-09-26

申请人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

发明人： Peter Gregorius ,  Martin Streibl ,  Thomas Rickes

IPC分类号： H03D3/24

CPC分类号： H03L7/087 ,  H03L7/091 ,  H03L7/0994 ,  H03L7/0995 ,  H03L7/113 ,  H03L7/18

摘要： A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

摘要翻译： 提供具有降低的固有噪声的锁相环。 锁相环包括受控振荡器，用于作为控制信号的结果输出周期性输出信号; 反馈单元，用于提供至少两个周期性反馈信号，所述至少两个周期性反馈信号具有彼此恒定的相移并且各自取决于输出信号 相位/频率检测器，用于根据周期性输入信号和至少一个反馈信号提供差分信号; 以及根据差分信号将控制信号提供给受控振荡器的控制电路。

公开(公告)号：US07173993B2

公开(公告)日：2007-02-06

申请号：US10219275

申请日：2002-08-16

申请人： Bernhard Engl ,  Peter Gregorius

发明人： Bernhard Engl ,  Peter Gregorius

IPC分类号： H04L7/00 ,  H03D3/24

CPC分类号： H04L7/007 ,  H04L7/0334 ,  H04L7/0337

摘要： Method for sampling phase control for clock and data recovery of a data signal includes sampling a received data signal with a first sampling signal comprising equidistant sampling pulses, minimizing phase deviation between the first sampling signal and the phase of the received data signal to generate an adjusted second sampling signal, and sampling the received data signal with the adjusted second sampling signal to generate sampling data values. The method also includes integrating the sampling data values of the sampled data signal to form a summation value, and altering the phase of sampling pulses of the adjusted second sampling signal until the integrated summation value exceeds a threshold value that can be set.

摘要翻译： 用于采样数据信号的时钟和数据恢复的相位控制的方法包括用包括等距采样脉冲的第一采样信号对接收的数据信号进行采样，使得第一采样信号和接收的数据信号的相位之间的相位偏移最小化，以产生经调整的 第二采样信号，并且用经调整的第二采样信号对接收到的数据信号进行采样以产生采样数据值。 该方法还包括对采样数据信号的采样数据值进行积分以形成求和值，并改变调整后的第二采样信号的采样脉冲的相位，直到积分和值超过可设定的阈值。

公开(公告)号：US20060181956A1

公开(公告)日：2006-08-17

申请号：US11046160

申请日：2005-01-28

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： One embodiment of the present invention provides a memory device comprising an array of memory cells, a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface, an input/output section for exchanging data, address and control signals with a circuit external to the memory device, the input/output section comprising a second interface for sending signals to and receiving signals from the first interface of the control logic, and a synchronizing facility connected to the first interface of the control logic and to the second interface of the input/output section for synchronizing the first interface of the control logic and the second interface of the input/output section.

摘要翻译： 本发明的一个实施例提供了一种存储器件，包括存储器单元阵列，用于将数据写入存储器单元阵列并从存储器单元阵列读取数据的控制逻辑，该控制逻辑包括第一接口，用于交换数据的输入/输出部分 ，具有存储器件外部电路的地址和控制信号，所述输入/输出部分包括用于向控制逻辑的第一接口发送信号并从其接收信号的第二接口，以及连接到控制逻辑的第一接口的同步设备 控制逻辑和输入/输出部分的第二接口，用于使控制逻辑的第一接口和输入/输出部分的第二接口同步。

公开(公告)号：US07088976B2

公开(公告)日：2006-08-08

申请号：US10492390

申请日：2002-09-04

申请人： Peter Gregorius ,  Torsten Hinz

发明人： Peter Gregorius ,  Torsten Hinz

IPC分类号： H04B1/06 ,  H04B7/00

CPC分类号： H04L7/033 ,  H04L7/0083

摘要： In a transceiver which is configured in particular for transmitting optical data, there is provided a device for reconstructing data from a received data signal (RX), having a clock-signal recovery unit (3) for recovering a clock signal belonging to the transmitted data from the received data signal, and having a data reconstruction unit (2) for reconstructing the transmitted data from the received data signal using the recovered clock signal (fCLK), and for emitting a data stream (DATA) which is synchronised with the recovered clock signal. A detector unit (9) detects an error state in the received data signal (RX) which prevents the data from being reconstructed reliably, switching means having a digital phase-locked lock (13) being provided to enable a signal having a clock rate which corresponds to the mean value of the clock signal (fCLK) previously recovered by the clock-signal recovery unit (3) to be fed, as a reference signal, to a phase-locked loop of the clock-signal recovery unit (3) in this event in place of the received data signal, thus ensuring that the phase-locked loop of the clock-signal recovery unit (3) will continue to oscillate properly even in this event.

摘要翻译： 在特别用于发送光数据的收发器中，提供了一种用于从接收的数据信号（RX）重建数据的装置，具有用于恢复属于发送数据的时钟信号的时钟信号恢复单元（3） 并且具有数据重建单元（2），用于使用恢复的时钟信号（f CLK）从接收到的数据信号重建发送的数据，并且用于发射数据流（DATA ）与恢复的时钟信号同步。 检测器单元（9）检测接收到的数据信号（RX）中的错误状态，其阻止数据被可靠地重建，具有数字锁相锁（13）的开关装置被提供以使得具有时钟速率的信号 对应于由时钟信号恢复单元（3）预先恢复的作为参考信号的时钟信号（f CLK）的平均值到时钟的锁相环 在这种情况下，信号恢复单元（3）代替接收到的数据信号，从而确保即使在这种情况下时钟信号恢复单元（3）的锁相环仍将适当地振荡。

公开(公告)号：US20060049967A1

公开(公告)日：2006-03-09

申请号：US11213550

申请日：2005-08-26

申请人： Andreas Jakobs ,  Peter Gregorius

发明人： Andreas Jakobs ,  Peter Gregorius

IPC分类号： H03M7/00

CPC分类号： H04J13/16

摘要： A code driver is described having a codeword source, which has n>1 source terminals and is designed to output at these terminals a sequence of n-digit codewords, each in the form of n parallel code characters, and having n parallel transmission paths between the n source terminals and n transmit terminals for sending the message represented by the codewords to a receiver. According to the invention, a selection device is provided, which indicates explicitly for each codeword which of the n digits of the codeword concerned are relevant to the decoding of the message in the receiver, and which, dependent on this explicit indication, activates only those of the n transmission paths that are assigned to the relevant digits of the codeword.

摘要翻译： 描述了具有代码字源的代码驱动器，其具有n≥1个源极端子，并且被设计为在这些端子处输出n个数字码字序列，每个n个码字码字以n个并行码字符的形式，并且具有n个并行传输路径， n个源终端和n个发送终端，用于将由码字表示的消息发送到接收机。 根据本发明，提供了一种选择装置，其针对每个码字明确地指示所涉及的码字的n位的哪一个与接收机中的消息的解码相关，并且根据该显式指示仅激活那些 分配给码字的相关数字的n个传输路径。

公开(公告)号：US20050111591A1

公开(公告)日：2005-05-26

申请号：US10970516

申请日：2004-10-21

申请人： Peter Gregorius ,  Paul Georg Lindt ,  Heinz Mattes

发明人： Peter Gregorius ,  Paul Georg Lindt ,  Heinz Mattes

IPC分类号： H03D1/00 ,  H04B17/00 ,  H04L1/20 ,  H04L12/26 ,  H04L12/56 ,  H04L25/02 ,  H04L25/08

CPC分类号： H04L47/10

摘要： To estimate physical properties of a wired or wireless transmission channel it is proposed to sample a signal, received via the transmission channel, for example a system response of the corresponding transmission system, in order, on the basis of the sampled values thus obtained, to ascertain the moments of the order 0 . . . n of the received signal. Using these moments of the order 0 . . . n, n parameters of a transmission function of the transmission channel can be determined, wherein the parameters can be polynomial coefficients, zero points or coefficients of a residual notation of the transmission function. Using this transmission function the physical properties of the transmission channel, such as the attenuation and dispersion properties, can be determined exactly or at least approximately assessed.

摘要翻译： 为了估计有线或无线传输信道的物理特性，提出了通过传输信道接收的信号，例如相应传输系统的系统响应，以这样获得的采样值为基础 确定订单的时刻0。 。 。 n的接收信号。 使用订单0的这些时刻。 。 。 可以确定传输信道的传输函数的n，n个参数，其中参数可以是传输函数的多项式系数，零点或残差符号的系数。 使用这种传输功能，传输通道的物理特性，如衰减和色散特性，可以精确地或至少近似评估来确定。

公开(公告)号：US06710603B2

公开(公告)日：2004-03-23

申请号：US10090318

申请日：2002-03-04

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G01R3108

CPC分类号： H03K17/6872 ,  H03K17/0822

摘要： A detection circuit is described which is configured, in particular, for line drivers for ascertaining the presence of an overshooting of a current flowing through a line above a predetermined value. The detection circuit has two current mirrors, in each case the input of one current mirror being connected to the output of the other current mirror. If the current feeds one current mirror, then an overshooting of the predetermined value can be ascertained on the basis of an output signal of the other current mirror.

摘要翻译： 描述了一种检测电路，其特别地被配置用于线路驱动器，用于确定流过高于预定值的线路的电流的过冲。 检测电路具有两个电流镜，每种情况下，一个电流镜的输入端连接到另一个电流镜的输出端。 如果电流馈送一个电流镜，则可以基于另一电流镜的输出信号来确定预定值的过冲。

公开(公告)号：US08144755B2

公开(公告)日：2012-03-27

申请号：US11947339

申请日：2007-11-29

申请人： Michael Bruennert ,  Christoph Bilger ,  Peter Gregorius ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

发明人： Michael Bruennert ,  Christoph Bilger ,  Peter Gregorius ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

IPC分类号： H04B3/46

CPC分类号： H04L25/03878 ,  H04L1/0047 ,  H04L1/0057 ,  H04L1/20

摘要： The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

摘要翻译： 本发明提供了一种用于确定接收机经由来自发射机的接口接收的编码数据字的每个数据位的偏斜的方法和装置，包括以下步骤：对所接收和采样的编码数据字执行错误检查和校正， 计算对应于由发送器发送的编码数据字的纠错编码数据字，并将纠错编码数据字序列与采样编码数据字进行相关，以确定所接收编码数据字的每个数据位的偏斜。

公开(公告)号：US07920433B2

公开(公告)日：2011-04-05

申请号：US11971819

申请日：2008-01-09

申请人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

发明人： Christoph Bilger ,  Peter Gregorius ,  Michael Bruennert ,  Maurizio Skerlj ,  Wolfgang Walthes ,  Johannes Stecker ,  Hermann Ruckerbauer ,  Dirk Scheideler ,  Roland Barth

IPC分类号： G11C7/06

CPC分类号： G11C7/1006

摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

摘要翻译： 涉及包括多个存储器单元的存储设备的方法和装置，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元 和第二数据路径，以及逻辑单元。 逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。 当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。 此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。 另外，提供了一种用于制造存储器件的方法。