公开(公告)号：US20140167817A1

公开(公告)日：2014-06-19

申请号：US14188734

申请日：2014-02-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: H03K19/00 ,  H01L25/00 ,  H03K19/177

CPC classification number: H03K19/0013 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/177 ,  H03K19/17744 ,  H01L2924/00

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract translation: 可编程模拟设备和模拟设备即使在供电电源中断并且功耗较低时也能保留数据。 在半导体器件中，第一至第四晶体管用作包括模拟元件的单元的开关，并且单元的输出通过模拟元件通过模拟元件在导通状态，非导通状态和导通状态之间切换， 控制第一晶体管和第二晶体管连接的第一节点的电位以及第三晶体管和第四晶体管连接的第二节点的电位。

公开(公告)号：US20140009199A1

公开(公告)日：2014-01-09

申请号：US13928590

申请日：2013-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Hidetomo Kobayashi

IPC: H03K3/012

CPC classification number: H03K17/687 ,  G11C5/005 ,  G11C5/148 ,  G11C11/403 ,  G11C11/4076 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1207 ,  H03K3/012 ,  H03K3/356008

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract translation: 提供了一种新颖的半导体器件及其驱动方法。 在半导体器件中，通过适当的算术处理保存的数据和存储数据的节点的（易失性）节点通过沟道形成在氧化物半导体中的晶体管的源极和漏极电连接 层。 晶体管的截止电流值极低。 因此，即使在停止供给电源电压的期间，电荷几乎不会从后一个节点通过晶体管泄漏，因此数据也可以被保持在后一个节点中。 在半导体装置中，提供将后一个节点的电位设定为预定电位的装置。 具体地说，提供了从前一个节点提供与后一个节点中存储的数据相对应的“1”或“0”的电位的装置。

公开(公告)号：US20140009198A1

公开(公告)日：2014-01-09

申请号：US13928555

申请日：2013-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: H03K3/356

CPC classification number: H03K3/356008 ,  G11C5/148 ,  G11C11/401 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/012 ,  H03K3/0375

Abstract: A novel semiconductor device and a method of driving the semiconductor device. A (volatile) node in which data that is rewritten as appropriate by arithmetic processing is held and a node in which the data is stored are electrically connected to each other via a source and a drain of a transistor in which a channel is formed in an oxide semiconductor layer. Then, data and data obtained by inverting the data (inverted data) are stored before supply of power source voltage is stopped, and the two inputs (data) are compared after restart of supply of the power source voltage, so that data obtained by arithmetic processing just before the supply of the power source voltage is stopped is restored.

Abstract translation: 一种新型半导体器件和驱动该半导体器件的方法。 保持通过算术处理适当地重写的数据的数据被保存并且其中存储数据的节点经由其中在其中形成通道的晶体管的源极和漏极彼此电连接的（易失性）节点 氧化物半导体层。 然后，在供给电源电压停止之前存储反转数据（反转数据）而获得的数据和数据，并且在重新开始电源电压的重新开始之后比较两个输入（数据），使得通过算术获得的数据 恢复在电源电压供应停止之前的处理。

公开(公告)号：US20130285049A1

公开(公告)日：2013-10-31

申请号：US13868270

申请日：2013-04-23

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Atsushi Miyaguchi

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1225

Abstract: A standard cell and a semiconductor integrated circuit which enable a reduction in layout area are provided. A power source line for supplying a high power source potential and a power source line for supplying a low power source potential are arranged in the same wiring layer, and a power source line for supplying a back-gate electrode with a voltage for controlling a threshold voltage is provided to overlap with one of the two power source lines. Further, standard cells each requiring a different number of power source lines are arranged in the same cell row, and a different number of power source lines are connected to each cell row, whereby the number of unnecessary power source lines is reduced so that layout area is reduced.

Abstract translation: 提供了能够减少布局面积的标准单元和半导体集成电路。 用于提供高电源电位的电源线和用于提供低电源电位的电源线布置在同一布线层中，以及用于向后栅电极提供用于控制阈值的电压的电源线 提供电压以与两个电源线之一重叠。 此外，每个要求不同数量的电源线的标准单元被布置在相同的单元行中，并且不同数量的电源线被连接到每个单元行，由此减少了不必要的电源线的数量，使得布局面积 降低了。