公开(公告)号：US10373991B2

公开(公告)日：2019-08-06

申请号：US15230727

申请日：2016-08-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Naoto Kusumoto ,  Kentaro Hayashi

IPC: H04N5/232 ,  H04N5/347 ,  H04N5/369 ,  H01L27/146 ,  H04N5/3745

Abstract: An imaging device with low power consumption is provided. The pixel of the imaging device includes first and second photoelectric conversion elements, and first to fifth transistors. A cathode of the first photoelectric conversion element is electrically connected to the first transistor. An anode of a second photoelectric conversion element is electrically connected to the second transistor. Imaging data of a reference frame is obtained using the first photoelectric conversion element, and then imaging data of a difference detection frame is obtained using the second photoelectric conversion element. After the imaging data of the difference detection frame is obtained, a first potential that is a potential of a signal output from the pixel and a second potential that is a reference potential are compared. Whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined using the first potential and the second potential.

公开(公告)号：US10043833B2

公开(公告)日：2018-08-07

申请号：US15293488

申请日：2016-10-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Seiichi Yoneda ,  Takuro Ohmaru

IPC: H01L27/08 ,  H01L27/12 ,  H01L29/78 ,  H01L27/06 ,  H01L29/786 ,  H01L29/04 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor which includes a first gate electrode below its oxide semiconductor layer and a second gate electrode above its oxide semiconductor layer, and a second transistor which includes a first gate electrode above its oxide semiconductor layer and a second gate electrode below its oxide semiconductor layer and is provided so as to at least partly overlap with the first transistor. In the semiconductor device, a conductive film serving as the second gate electrode of the first transistor and the second gate electrode of the second transistor is shared between the first transistor and the second transistor. Note that the second gate electrode not only controls the threshold voltages (Vth) of the first transistor and the second transistor but also has an effect of reducing interference of an electric field applied from respective first gate electrodes of the first transistor and the second transistor.

公开(公告)号：US09496022B2

公开(公告)日：2016-11-15

申请号：US14723613

申请日：2015-05-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/401 ,  G11C29/24 ,  G11C29/42 ,  G11C29/50 ,  G11C11/404 ,  G11C5/14

CPC classification number: G11C11/406 ,  G11C5/147 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4076 ,  G11C29/24 ,  G11C29/42 ,  G11C29/50016

Abstract: To provide a novel semiconductor device. The semiconductor device includes a circuit including a memory cell including a transistor using an oxide semiconductor; and a refresh timing determination unit including a capacitor, a transistor using an oxide semiconductor, and a comparator circuit. The potential of a floating node in the refresh timing determination unit is directly or indirectly input to the comparator circuit and compared with a reference potential. When the potential of the floating node becomes a certain value, a power switch operating in accordance with an output of the comparator circuit is turned on, power is supplied to the circuit including the memory cell, and then the reference potential is also changed. After that, refresh operation of the memory cell is performed. When the refresh operation is finished, the power switch is turned off.

Abstract translation: 提供一种新型的半导体器件。 该半导体器件包括：包括具有使用氧化物半导体的晶体管的存储单元的电路; 以及包括电容器，使用氧化物半导体的晶体管和比较器电路的刷新定时确定单元。 刷新定时确定单元中的浮动节点的电位直接或间接地输入到比较器电路并与参考电位进行比较。 当浮动节点的电位变为特定值时，根据比较器电路的输出操作的电源开关导通，向包括存储单元的电路供电，然后参考电位也改变。 之后，执行存储单元的刷新操作。 刷新操作完成后，电源开关关闭。

公开(公告)号：US09490806B2

公开(公告)日：2016-11-08

申请号：US14726754

申请日：2015-06-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru

IPC: H03K19/094 ,  H01L25/00 ,  H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0013 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/177 ,  H03K19/17744 ,  H01L2924/00

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

公开(公告)号：US09257971B2

公开(公告)日：2016-02-09

申请号：US14541305

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C7/00 ,  G11C8/00 ,  H03K3/356 ,  H03K21/02 ,  H03K21/40 ,  H03K3/012

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.

Abstract translation: 半导体器件包括第一锁存器，第二锁存器和半导体层包含氧化物半导体的晶体管。 第一锁存器的输入电连接到晶体管的源极和漏极中的一个，第一锁存器的输出电连接到第二锁存器的输入，并且第二锁存器的输出电连接到 晶体管的源极或漏极中的另一个。

公开(公告)号：US20150295577A1

公开(公告)日：2015-10-15

申请号：US14726754

申请日：2015-06-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru

IPC: H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0013 ,  H01L25/00 ,  H01L2924/0002 ,  H03K19/177 ,  H03K19/17744 ,  H01L2924/00

Abstract: A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.

Abstract translation: 可编程模拟设备和模拟设备即使在供电电源中断并且功耗较低时也能保留数据。 在半导体器件中，第一至第四晶体管用作包括模拟元件的单元的开关，并且单元的输出通过模拟元件通过模拟元件在导通状态，非导通状态和导通状态之间切换， 控制第一晶体管和第二晶体管连接的第一节点的电位以及第三晶体管和第四晶体管连接的第二节点的电位。

公开(公告)号：US20150235700A1

公开(公告)日：2015-08-20

申请号：US14702817

申请日：2015-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: G11C14/00 ,  G11C11/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/24 ,  H01L27/108

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract translation: 提供能够抑制功耗的信号处理电路。 在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。 通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。 因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。 可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。 因此，可以准确地读取原始信号。

公开(公告)号：US09007816B2

公开(公告)日：2015-04-14

申请号：US13683257

申请日：2012-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru

IPC: G11C11/00 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/00 ,  G11C11/412

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

Abstract translation: 为了降低功耗，存储电路包括：锁存单元，其中根据控制信号重写和读取第一数据和第二数据;第一开关单元，其通过以下步骤控制对存储在锁存单元中的第一数据的重写和读取： 响应于所述控制信号而导通或断开;以及第二开关单元，其响应于所述控制信号而导通或关断控制存储在所述锁存单元中的所述第二数据的重写和读取。 闩锁单元包括第一反相器和第二反相器。 第一反相器和第二反相器中的至少一个包括第一场效应晶体管和第二场效应晶体管，其具有与第一场效应晶体管相同的导电类型并且具有根据控制的栅极电位 信号。

公开(公告)号：US08988152B2

公开(公告)日：2015-03-24

申请号：US13768743

申请日：2013-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Shuhei Nagatsuka

IPC: H03K3/03 ,  H01L29/786 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/088 ,  H01L27/1225 ,  H03K3/0315 ,  H03K19/0013 ,  H03K19/20 ,  H03K2005/00032 ,  H03K2005/00195 ,  H03K2217/0018

Abstract: To provide a semiconductor device including an inverter circuit whose driving frequency is increased by control of the threshold voltage of a transistor or a semiconductor device including an inveter circuit with low power consumption. An inverter circuit includes a first transistor and a second transistor each including a semiconductor film in which a channel is formed, a pair of gate electrodes between which the semiconductor film is placed, and source and drain electrodes in contact with the semiconductor film. Controlling potentials applied to the pair of gate electrodes makes the first transistor have normally-on characteristics and the second transistor have normally-off characteristics. Thus, the driving frequency of the inverter circuit is increased.

Abstract translation: 为了提供一种半导体器件，其包括通过控制晶体管的阈值电压或包括具有低功耗的入侵电路的半导体器件来驱动驱动频率的逆变器电路。 逆变器电路包括第一晶体管和第二晶体管，每个晶体管和第二晶体管都包括其中形成沟道的半导体膜，放置半导体膜的一对栅极电极和与半导体膜接触的源极和漏极。 施加到一对栅电极的控制电位使得第一晶体管具有常开特性，而第二晶体管具有常关特性。 因此，逆变器电路的驱动频率增加。

公开(公告)号：US20150070962A1

公开(公告)日：2015-03-12

申请号：US14479707

申请日：2014-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Kiyoshi Kato

IPC: G11C5/14 ,  G11C5/06

CPC classification number: G11C5/14 ,  G11C11/403 ,  H01L27/1225 ,  H01L27/1255

Abstract: To provide a memory device with short overhead time and a semiconductor device including the memory device. A memory device includes a first circuit that can retain data and a second circuit by the supply of power supply voltage. The second circuit includes a third circuit that selects a first potential corresponding to the data or a second potential supplied to a first wiring; a first transistor having a channel formation region in an oxide semiconductor film; a capacitor that hold the first potential or the second potential that is selected by the third circuit and supplied through the first transistor; and a second transistor controlling a conduction state between the first circuit and a second wiring that can supply a third potential in accordance with the potential retained in the capacitor.

Abstract translation: 提供具有较短开销时间的存储器件和包括存储器件的半导体器件。 存储器件包括通过提供电源电压可以保留数据的第一电路和第二电路。 第二电路包括第三电路，其选择对应于数据的第一电位或提供给第一布线的第二电位; 在氧化物半导体膜中具有沟道形成区域的第一晶体管; 保持由第三电路选择并通过第一晶体管提供的第一电位或第二电位的电容器; 以及第二晶体管，其控制所述第一电路和第二布线之间的导通状态，所述第二布线可以根据保持在所述电容器中的电位提供第三电位。