Method for measuring quantity of usage of CPU
    71.
    发明授权
    Method for measuring quantity of usage of CPU 有权
    测量CPU使用量的方法

    公开(公告)号:US07412354B2

    公开(公告)日:2008-08-12

    申请号:US11410834

    申请日:2006-04-26

    IPC分类号: G06F15/00

    摘要: The present invention relates to a method for measuring a quantity of usage of a CPU, in particular to a method for measuring a quantity of usage of a CPU which is capable of getting a credible quantity of usage of a CPU without amending an algorithm in order to adapt it to the an operating system, e.g., MS-Windows System, or requiring a complicated code. The method uses various algorithms provided by the operating system on the behalf of a registry storing a quantity of usage of a CPU inside a system. Accordingly the present invention can measure a quantity of usage of a CPU easily without lowering a performance of the operating system.

    摘要翻译: 本发明涉及一种用于测量CPU使用量的方法,特别涉及一种用于测量CPU使用量的方法,该方法能够获得CPU的可靠数量的使用量,而无需按顺序修改算法 以适应操作系统,例如MS-Windows系统,或需要复杂的代码。 该方法使用由操作系统提供的各种算法,代表存储系统内CPU使用量的注册表。 因此,本发明可以容易地测量CPU的使用量而不降低操作系统的性能。

    System and method for controlling duplexing in an ATM switching system
    73.
    发明授权
    System and method for controlling duplexing in an ATM switching system 失效
    用于在ATM交换系统中控制双工的系统和方法

    公开(公告)号:US07203160B1

    公开(公告)日:2007-04-10

    申请号:US09666054

    申请日:2000-09-20

    申请人: Sang Ho Lee

    发明人: Sang Ho Lee

    IPC分类号: G01R31/08

    CPC分类号: H04L43/0817

    摘要: A duplexing control system and method of an ATM switching system capable of carrying out a stable switching of duplexing with a simple circuit construction is disclosed. The system has two boards respectively having a first interface matching with an input bus so as to interface received ATM cell, a second interface matching with an output bus so as to interface a transmitted ATM cell, an SAR for disassembling and assembling data units contained in an application layer in the transmitted/received ATM cell by a unit of ATM cell, a control section for controlling general operation in order to maintain the active state according to data processing information contained in a signal applied from the cell disassembling and assembling circuit, when the its own board is endowed with the active authority by the signal, and a DRAM for storing data transmitted/received for the switching of duplexing between the boards. The duplexing control system and method in an ATM system causes data processing information of one board and a duplexing authority to be formed into an ATM cell and to be transferred through a cell bus, so that a duplexing control can be stably carried out.

    摘要翻译: 公开了一种能够以简单的电路结构实现双工的稳定切换的ATM交换系统的双工控制系统和方法。 该系统具有两个板,分别具有与输入总线匹配的第一接口,以便接收接收到的ATM信元,与输出总线匹配的第二接口,以便接收所发送的ATM信元,用于拆卸和组合包含在其中的数据单元 通过ATM信元单元发送/接收的ATM信元中的应用层,控制部分,用于控制一般操作,以便根据包含在从信元拆卸和组装电路施加的信号中的数据处理信息来保持活动状态,当时 其自己的板被信号赋予主动权限,以及用于存储用于在板之间切换双工的发送/接收数据的DRAM。 ATM系统中的双工控制系统和方法使一个电路板和双工部门的数据处理信息形成为一个ATM信元,并通过一个信元总线进行传输,从而可以稳定地进行双工控制。

    Counter circuit for embodying linear burst sequence
    75.
    发明授权
    Counter circuit for embodying linear burst sequence 失效
    用于体现线性突发序列的计数器电路

    公开(公告)号:US5966420A

    公开(公告)日:1999-10-12

    申请号:US908571

    申请日:1997-08-08

    申请人: Sang Ho Lee

    发明人: Sang Ho Lee

    IPC分类号: G11C11/413 H03K21/00

    CPC分类号: H03K21/00

    摘要: A counter circuit uses a plurality of counter circuits so as to be used in all products employing a counter circuit in a semiconductor device, and thereby performs a multi-bit linear burst sequence operation. The counter circuit for embodying a linear burst sequence includes: a low order counting means which responds to an external clock signal and an external counting control signal, receives and counts a least significant first bit data among base input signals having bits ranging from a first bit to a N-th bit, and then generates a first data signal and a first high order control signal; and a plurality of high order counting means which receive bits ranging from a second bit successively connected to the least significant first bit to N-th bit, perform a counting operation, and generate a second data signal and a second high order control signal. The high order counting means which responds to the high order control signal and the counting control signal which are generated from the high order counting means of a previous bit of a present input bit, performs a counting operation, and outputs data signal.

    摘要翻译: 计数器电路使用多个计数器电路,以便在半导体器件中采用计数器电路的所有产品中使用,从而执行多位线性突发序列操作。 用于实现线性突发序列的计数器电路包括:响应于外部时钟信号的一个低阶计数装置和一个外部计数控制信号,在基本输入信号中接收和计数最低有效的第一位数据,该基本输入信号具有从第一位 到第N位,然后产生第一数据信号和第一高阶控制信号; 以及多个高阶计数装置,其接收从连续连接到最低有效第一比特到第N比特的第二比特的比特,执行计数操作,并产生第二数据信号和第二高阶控制信号。 响应于从当前输入位的先前位的高位计数装置产生的高阶控制信号和计数控制信号的高阶计数装置执行计数操作,并输出数据信号。

    Read/write control circuit for semiconductor memory device
    76.
    发明授权
    Read/write control circuit for semiconductor memory device 失效
    半导体存储器件的读/写控制电路

    公开(公告)号:US5877988A

    公开(公告)日:1999-03-02

    申请号:US901433

    申请日:1997-07-25

    CPC分类号: G11C7/1078 G11C7/22

    摘要: A write error preventing circuit for a semiconductor memory device prevents an erroneous reading operation an input buffer compares an externally applied write enable signal to an effective level signal, which is preset therein. A write error preventive circuit outputs a disable signal to the input buffer during an interval of time when a ground voltage bounces in accordance with an internal output signal from a NAND gate of an output buffer. The circuit prevents the outputting of a write signal from the input buffer during a read operation in accordance with the internal output signal from the output buffer when the ground voltage bounces.

    摘要翻译: 用于半导体存储器件的写入错误防止电路防止错误读取操作,输入缓冲器将外部施加的写使能信号与其中预设的有效电平信号进行比较。 写入错误防止电路在接地电压根据来自输出缓冲器的与非门的内部输出信号反弹的时间间隔期间向输入缓冲器输出禁止信号。 当接地电压反弹时,该电路根据来自输出缓冲器的内部输出信号,在读取操作期间防止从输入缓冲器输出写入信号。

    Recombinant mycobacterial methionyl-tRNA synthetase genes and methods of
use therefore
    77.
    发明授权
    Recombinant mycobacterial methionyl-tRNA synthetase genes and methods of use therefore 失效
    重组分枝杆菌甲硫氨酰-tRNA合成酶基因及其使用方法

    公开(公告)号:US5798240A

    公开(公告)日:1998-08-25

    申请号:US584226

    申请日:1996-01-11

    摘要: Isolated and/or recombinant nucleic acids encoding mycobacterial methionyl-tRNA synthetase have been characterized. Recombinant DNA constructs and vectors having a sequence which encodes mycobacterial methionyl-tRNA synthetase have been made, and can be used for the construction of tester strains as well as for the production of isolated and/or recombinant methionyl-tRNA synthetases. These enzymes or portions thereof are useful in the biochemical separation of methionine and quantification of methionine or ATP, and for producing antibodies useful in the purification and study of the enzyme, for example. Host cells and methods useful for producing recombinant mycobacterial methionyl-tRNA synthetases are described, as are tester strains, which are cells engineered to rely on the function of the tRNA synthetase encoded by an introduced cloned gene. Tester strains can be used to identify inhibitors of the essential tRNA synthetase enzyme encoded by the introduced cloned gene, and thus provide a means to assess the antimicrobial effect and specificity of the inhibitor without employing slow-growing, pathogenic strains of mycobacteria, such as Mycobacterium tuberculosis.

    摘要翻译: 已经表征了编码分枝杆菌甲硫氨酰-tRNA合成酶的分离和/或重组核酸。 已经制备了具有编码分枝杆菌甲硫氨酰-tRNA合成酶的序列的重组DNA构建体和载体,并且可用于构建测试菌株以及用于分离和/或重组甲硫氨酰-tRNA合成酶的产生。 这些酶或其部分可用于甲硫氨酸的生物化学分离和甲硫氨酸或ATP的定量,以及用于产生用于纯化和研究酶的抗体。 描述了可用于产生重组分枝杆菌甲硫氨酰-tRNA合成酶的宿主细胞和方法,试验菌株是被依赖于引入的克隆基因编码的tRNA合成酶的功能而被工程化的细胞。 测试菌株可以用于鉴定由引入的克隆基因编码的必需tRNA合成酶的抑制剂,并且因此提供了评估抑制剂的抗微生物效果和特异性的方法,而不使用分枝杆菌的缓慢生长的致病菌株,例如分枝杆菌 结核。

    Column repair circuit for integrated circuits
    78.
    发明授权
    Column repair circuit for integrated circuits 失效
    集成电路列修复电路

    公开(公告)号:US5689464A

    公开(公告)日:1997-11-18

    申请号:US600599

    申请日:1994-04-19

    CPC分类号: G11C29/812 G11C29/846

    摘要: A column repair circuit for a semiconductor memory having an input/output selection circuit for inputting a control signal, selecting a bit line and a bit bar line corresponding to a faulty memory cell and replacing the selected bit line and bit bar line with a spare bit line and a spare bit bar line. The input/output selection circuit includes an input stage for inputting the control signal, a spare bit line and a spare bit bar line, and a plurality of fuses each having one side connected to the input stage and other side connected to a plurality of resistors. The other side of the resistors are connected to ground for outputting the output signals. The input/output selection circuit further has a plurality of n-channel MOSFETs each including a gate connected to each of the other stages of the plurality of fuses via the resistors in a 2 to 1 manner for inputting the output signals. The drains of the MOSFETS are connected to the spare bit line and spare bit bar line and their sources are connected to each of the plurality of data bit lines and the plurality of data bit bar lines for functioning as a switch. Therefore, the present invention can provide the column repair circuit for a semiconductor memory which is capable of increasing its repair yield by adding the input/output selecting circuit enabling input/output selecting.

    摘要翻译: 一种用于半导体存储器的列修复电路,具有用于输入控制信号的输入/输出选择电路,选择与故障存储器单元相对应的位线和位线,并用备用位替换所选位线和位线 线和备用位线。 输入/输出选择电路包括用于输入控制信号的输入级,备用位线和备用位线条,以及多个熔丝,每个熔丝具有连接到输入级的一侧和连接到多个电阻器的另一侧 。 电阻的另一侧连接到地,用于输出输出信号。 所述输入/输出选择电路还具有多个n沟道MOSFET,每个n沟道MOSFET包括通过所述电阻器以多个熔丝连接到所述多个熔丝中的每一个的栅极,以2:1的方式输入所述输出信号。 MOSFETS的漏极连接到备用位线和备用位线,并且它们的源极连接到用作开关的多个数据位线和多个数据位线中的每一个。 因此,本发明可以提供半导体存储器的列修复电路,该半导体存储器能够通过添加能够进行输入/输出选择的输入/输出选择电路来提高其修复产率。

    Speech recognition system and method based on word-level candidate generation
    79.
    发明授权
    Speech recognition system and method based on word-level candidate generation 有权
    基于词级候选生成的语音识别系统和方法

    公开(公告)号:US09002708B2

    公开(公告)日:2015-04-07

    申请号:US13466700

    申请日:2012-05-08

    CPC分类号: G10L15/22 G10L15/30

    摘要: A speech recognition system and method based on word-level candidate generation are provided. The speech recognition system may include a speech recognition result verifying unit to verify a word sequence and a candidate word for at least one word included in the word sequence when the word sequence and the candidate word are provided as a result of speech recognition. A word sequence displaying unit may display the word sequence in which the at least one word is visually distinguishable from other words of the word sequence. The word sequence displaying unit may display the word sequence by replacing the at least one word with the candidate word when the at least one word is selected by a user.

    摘要翻译: 提供了一种基于词级候选生成的语音识别系统和方法。 语音识别系统可以包括语音识别结果验证单元,用于当作为语音识别的结果提供单词序列和候选词时,验证单词序列和包含在单词序列中的至少一个单词的候选词。 字序列显示单元可以显示字序列,其中至少一个字在视觉上与单词序列的其他单词区分开。 当用户选择至少一个单词时,字序列显示单元可以通过用候选词替换至少一个单词来显示单词序列。

    Apparatus and method for controlling multimedia broadcast and multicast service based on user location
    80.
    发明授权
    Apparatus and method for controlling multimedia broadcast and multicast service based on user location 有权
    基于用户位置控制多媒体广播和多播服务的装置和方法

    公开(公告)号:US08902814B2

    公开(公告)日:2014-12-02

    申请号:US12974608

    申请日:2010-12-21

    摘要: Provided is a multimedia broadcast and multicast service controlling apparatus and method based on a user location. The multimedia broadcast and multicast service controlling apparatus may receive MCCH information, may periodically update a service list of a mobile terminal based on the received MCCH information, the service list listing services that are providable, may register a service in a pending list when the service is not included in the updated service list and is requested to be provided, and may provide the service registered in the pending list when the mobile terminal reaches a location where the mobile terminal may provide the service registered in the pending list.

    摘要翻译: 提供了一种基于用户位置的多媒体广播和多播服务控制装置和方法。 多媒体广播和多播服务控制装置可以接收MCCH信息,可以基于接收的MCCH信息周期性地更新移动终端的服务列表,可提供的服务列表列表服务可以在服务中注册服务在待处理列表中 不包括在更新的服务列表中并被请求提供,并且可以在移动终端到达移动终端可以提供登记在待决列表中的服务的位置时提供登记在待决列表中的服务。