公开(公告)号：US5292673A

公开(公告)日：1994-03-08

申请号：US883531

申请日：1992-05-15

申请人： Hiroshi Shinriki ,  Masayuki Nakata ,  Kiichiro Mukai

发明人： Hiroshi Shinriki ,  Masayuki Nakata ,  Kiichiro Mukai

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285

CPC分类号： H01L29/66575 ,  H01L29/6659 ,  H01L29/78391

摘要： When a MOSFET containing a tantalum pentoxide film as a gate insulating film is formed, ion implantation is applied such that the end of an insulating film containing a tantalum pentoxide film situates to the outside of a gate electrode to thereby form source and drain regions. This can effectively prevent troubles such as short-circuitting due to tantalum pentoxide film and a highly reliable MOSFET can be obtained without applying light oxidation.

摘要翻译： 当形成含有五氧化二钽膜作为栅极绝缘膜的MOSFET时，施加离子注入，使得含有五氧化二钽膜的绝缘膜的端部位于栅电极的外部，从而形成源区和漏区。 这可以有效地防止由于五氧化二铝膜引起的短路等麻烦，并且可以在不施加光氧化的情况下获得高可靠性的MOSFET。

公开(公告)号：US4891684A

公开(公告)日：1990-01-02

申请号：US81231

申请日：1987-08-04

申请人： Yasushiro Nishioka ,  Hiroshi Shinriki ,  Noriyuki Sakuma ,  Kiichiro Mukai

发明人： Yasushiro Nishioka ,  Hiroshi Shinriki ,  Noriyuki Sakuma ,  Kiichiro Mukai

IPC分类号： H01L21/314 ,  H01G4/005 ,  H01G4/33 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/94 ,  H01G4/005 ,  H01G4/33 ,  H01L27/10805

摘要： A reaction-preventing film is provided between a capacitor insulating film made of a material having a high dielectric constant, such as Ta.sub.2 O.sub.5, and an upper electrode in order to prevent a reaction of the upper electrode with the capacitor insulating film. This effectively prevents the reaction between the upper electrode and the capacitor caused by a heat treatment conducted after formation of the capacitor, and hence prevents an increase in leakage current caused by the reaction. Thus, the reliability of a semiconductor device is remarkably increased.

摘要翻译： 为了防止上部电极与电容绝缘膜的反应，在由具有高介电常数的材料制成的电容器绝缘膜（例如Ta 2 O 5）和上部电极之间设置防反射膜。 这有效地防止了在形成电容器之后进行的热处理引起的上部电极和电容器之间的反应，从而防止了由反应引起的漏电流的增加。 因此，半导体器件的可靠性显着增加。

公开(公告)号：US4809052A

公开(公告)日：1989-02-28

申请号：US860413

申请日：1986-05-07

申请人： Yasushiro Nishioka ,  Takeo Shiba ,  Hiroshi Shinriki ,  Kiichiro Mukai ,  Akihisa Uchida ,  Ichiro Mitamura ,  Keiichi Higeta ,  Katsumi Ogiue ,  Kunihiko Yamaguchi ,  Noriyuki Sakuma

发明人： Yasushiro Nishioka ,  Takeo Shiba ,  Hiroshi Shinriki ,  Kiichiro Mukai ,  Akihisa Uchida ,  Ichiro Mitamura ,  Keiichi Higeta ,  Katsumi Ogiue ,  Kunihiko Yamaguchi ,  Noriyuki Sakuma

IPC分类号： G11C11/411 ,  H01L27/102 ,  H01L27/10 ,  H01L29/40 ,  H01L29/48

CPC分类号： G11C11/4116 ,  H01L27/1025

摘要： A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

摘要翻译： 提供半导体存储器件，例如具有触发器存储单元的类型，每个触发器存储单元包括彼此交叉连接的两个双极晶体管。 在某些实施例中，在数字线下形成存储单元中的肖特基势垒二极管或电容器的至少一部分。 该存储器件的所需面积大大降低，肖特基势垒二极管和电容器受数字线影响不大。 在其他实施例中，它被设置为为肖特基势垒二极管和电容器提供不同的电极，以在最小化的空间中优化结构。