利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23 条记录 (耗时 0.015 秒)

    Semiconductor integrated circuit device and method of manufacturing the same
    1.
    发明授权
    Semiconductor integrated circuit device and method of manufacturing the same 失效
    半导体集成电路器件及其制造方法

    公开(公告)号：US6034912A

    公开(公告)日：2000-03-07

    申请号：US145076

    申请日：1998-09-01

    申请人： Satoru Isomura ,  Atsushi Shimizu ,  Keiichi Higeta ,  Tohru Kobayashi ,  Takeo Yamada ,  Yuko Ito ,  Kengo Miyazawa ,  Kunihiko Yamaguchi

    发明人： Satoru Isomura ,  Atsushi Shimizu ,  Keiichi Higeta ,  Tohru Kobayashi ,  Takeo Yamada ,  Yuko Ito ,  Kengo Miyazawa ,  Kunihiko Yamaguchi

    IPC分类号： G11C5/02 ,  H01L27/02 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  G11C5/025 ,  H01L27/0207 ,  H03K19/1774 ,  H03K19/17792 ,  H03K19/17796

    摘要： A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits. Next, the clock signal is supplied to a plurality of third state clock distributing circuits equidistantly disposed from each of the second stage clock distributing circuits and then supplied to a plurality of final stage clock distributing circuits equidistantly disposed from each of the third stage clock distributing circuits. From these final stage clock distributing circuits, the clock signal is supplied to an area in whose units an internal gate array and a RAM macro cell or a logic macro cell are made replaceable with each other.

    摘要翻译： 半导体器件的存储部分和逻辑电路部分形成在单个半导体衬底上，其中第一逻辑电路块和第二逻辑电路块形成在不同的区域中，并且第二逻辑电路位于一对存储块之间 。 存储在一对存储器块中的数据被发送到第二逻辑电路块，以经由存储器外围电路进行处理。 经由第二逻辑电路块中提供的输入/输出电路将数据处理的结果发送到第一逻辑电路块或外部设备。 输入到半导体芯片的中心部分的时钟信号被提供给从中心部分等距设置的多个第一状态时钟分配电路，然后被提供给至少等距地从第一状态中的每个状态设置的多个第二级时钟分配电路 时钟分配电路。 接下来，时钟信号被提供给从每个第二级时钟分配电路等距离设置的多个第三状态时钟分配电路，然后提供给从每个第三级时钟分配电路等距设置的多个最后级时钟分配电路 。 从这些最终级时钟分配电路，将时钟信号提供给其单位内的内部门阵列和RAM宏小区或逻辑宏小区彼此可替换的区域。

    Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals
    3.
    发明授权
    Semiconductor circuit having a current switch circuit which imparts a latch function to an input buffer for generating high amplitude signals 失效
    具有电流开关电路的半导体电路，其向输入缓冲器提供锁存功能，用于产生高幅度信号

    公开(公告)号：US4727265A

    公开(公告)日：1988-02-23

    申请号：US755910

    申请日：1985-07-17

    申请人： Hiroaki Nanbu ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kazuo Kanetani ,  Goro Kitsukawa

    发明人： Hiroaki Nanbu ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kazuo Kanetani ,  Goro Kitsukawa

    IPC分类号： G11C11/414 ,  G11C11/41 ,  H03K17/30 ,  H03K17/60 ,  H03K17/62 ,  H03K17/693 ,  H03K17/16 ,  H03K19/00 ,  H03K19/092 ,  H03L5/00

    CPC分类号： H03K17/693 ,  H03K17/603 ,  H03K17/6292

    摘要： A semiconductor circuit of a current mode type logic is provided having a reference voltage generating circuit which generates the reference voltage to be applied to the logic circuit in response to a clock signal to latch the state corresponding to an input signal at an instant of the clock signal input. The reference voltage has three levels in response to the voltage levels of the clock signal and the input signal: a middle voltage between the two high and low voltage levels of the input signal when the clock signal is at a first level voltage; a voltage higher than the high voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a high voltage; and a voltage lower than the low voltage level of the input signal when the clock signal is at a second level voltage and the output signal is at a second level voltage and the output signal is at a low voltage. This semiconductor circuit can relax restrictions on the signal amplitude due to the supply voltage and the saturation of the transistors, and, accordingly, allows processing signals having a much greater amplitude than was previously possible.

    摘要翻译： 提供电流模式型逻辑的半导体电路，其具有参考电压产生电路，该参考电压产生电路响应于时钟信号产生要施加到逻辑电路的参考电压，以在时钟瞬间锁存对应于输入信号的状态 信号输入。 参考电压响应于时钟信号和输入信号的电压电平而具有三个电平：当时钟信号处于第一电平电压时，输入信号的两个高电平和低电平电平之间的中间电压; 当所述时钟信号处于第二电平电压并且所述输出信号处于高电压时，所述电压高于所述输入信号的高电压电平; 以及当所述时钟信号处于第二电平电压并且所述输出信号处于第二电平电压且所述输出信号处于低电压时，所述电压低于所述输入信号的低电压电平。 该半导体电路可以放宽由于晶体管的电源电压和饱和度导致的对信号幅度的限制，因此允许处理具有比之前可能的幅度大得多的信号。

    Temperature-compensated current source circuit and a reference voltage generating circuit using the same
    4.
    发明授权
    Temperature-compensated current source circuit and a reference voltage generating circuit using the same 失效
    温度补偿电流源电路和使用其的参考电压发生电路

    公开(公告)号：US4461992A

    公开(公告)日：1984-07-24

    申请号：US367676

    申请日：1982-04-12

    申请人： Kunihiko Yamaguchi ,  Noriyuki Homma

    发明人： Kunihiko Yamaguchi ,  Noriyuki Homma

    IPC分类号： G05F1/56 ,  G05F1/567 ,  G05F3/30 ,  G05F3/20

    CPC分类号： G05F1/567 ,  G05F3/30 ,  Y10S323/907

    摘要： A current source circuit includes a first and a second transistor connected at the collector to a common load resistor. In the current source circuit, the emiiters of the first and second transistors are connected to a negative power source through different current restricting resistors. The base of the first transistor is biased by a series circuit including two diodes. The temperature coefficients of the collector currents of the first and second transistors are offset, so that the temperature-compensated current flows into the load resistor.

    摘要翻译： 电流源电路包括在集电极处连接到公共负载电阻器的第一和第二晶体管。 在电流源电路中，第一和第二晶体管的发射器通过不同的电流限制电阻器连接到负电源。 第一晶体管的基极由包括两个二极管的串联电路偏置。 第一和第二晶体管的集电极电流的温度系数偏移，使得温度补偿电流流入负载电阻器。

    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
    集成电路中使用的半导体集成电路和半导体逻辑电路

    公开(公告)号：US06998878B2

    公开(公告)日：2006-02-14

    申请号：US10754596

    申请日：2004-01-12

    申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    IPC分类号： H03K19/20

    CPC分类号： G11C8/10

    摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

    摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中， 在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是 减少 利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期 增加。

    Dynamic random access memory including read preamplifiers activated before rewrite amplifiers
    9.
    发明授权
    Dynamic random access memory including read preamplifiers activated before rewrite amplifiers 失效
    动态随机存取存储器包括在重写放大器之前激活的读前置放大器

    公开(公告)号：US5587952A

    公开(公告)日：1996-12-24

    申请号：US391537

    申请日：1995-02-21

    申请人： Goro Kitsukawa ,  Takao Watanabe ,  Ryoichi Hori ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kiyoo Itoh

    发明人： Goro Kitsukawa ,  Takao Watanabe ,  Ryoichi Hori ,  Noriyuki Honma ,  Kunihiko Yamaguchi ,  Kiyoo Itoh

    IPC分类号： G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/409 ,  G11C7/06

    CPC分类号： G11C11/4087 ,  G11C11/4082 ,  G11C11/4091 ,  G11C11/4096

    摘要： A dynamic random access memory is provided which includes word lines for accessing memory cells, data lines for transferring information from the memory cells, and rewrite amplifiers connected to the data lines for rewriting the information to corresponding memory cells. Read pre-amplifiers are also provided for sensing the information, together with common data lines for transferring output signals of the read pre-amplifiers. Each of the read pre-amplifiers has two insulated gate field-effect transistors, gates of which are connected to the data lines, and sources/drains of which are connected with the common data lines, such that the common data lines do not form current paths with the data lines. In addition, the read pre-amplifiers are activated before the rewrite amplifiers.

    摘要翻译： 提供了一种动态随机存取存储器，其包括用于访问存储单元的字线，用于从存储器单元传送信息的数据线，以及连接到数据线的重写放大器，用于将信息重写到相应的存储器单元。 还提供读取前置放大器用于感测信息，以及公共数据线，用于传输读取的前置放大器的输出信号。 每个读取的预放大器具有两个绝缘栅场效应晶体管，其栅极连接到数据线，并且其源极/漏极与公共数据线连接，使得公共数据线不形成电流 路径与数据线。 此外，读取的前置放大器在重写放大器之前被激活。

    Memory cell and a memory device having reduced soft error
    10.
    发明授权
    Memory cell and a memory device having reduced soft error 失效
    存储单元和具有降低的软错误的存储器件

    公开(公告)号：US5523966A

    公开(公告)日：1996-06-04

    申请号：US530421

    申请日：1995-09-18

    申请人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    发明人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

    CPC分类号： G11C11/4125 ,  H01L27/11 ,  H01L27/1104

    摘要： Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.

    摘要翻译： 公开了一种具有高抗α射线诱导的软错误免疫力的静态型记忆体。 存储单元在两个数据存储节点1和2之间具有耦合电容Cc。其中形成驱动器MOS晶体管MN3，MN4和传输MOS晶体管MN1，MN2的p阱（或p衬底）连接到 一个Vbb发生器。 电压Vbb被设定为低于存储单元信号电位的低电平VL。 即使当低电压侧节点2的电位变化量DELTA VL大时，存在于与MN1-MN4的源极或漏极对应的n型扩散层与p阱（或p-衬底）之间的寄生二极管， 不打开 因此可以防止错误的操作。