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71.发明授权公开(公告)号：US12088013B2
公开(公告)日：2024-09-10
申请号：US17655248
申请日：2022-03-17
CPC分类号： H01Q21/065 , H01Q3/36 , H01Q21/28
摘要： Apparatus and methods for wirelessly communicating using antennas are disclosed. In certain embodiments, an antenna system includes a first radio frequency signal conditioning circuit configured to condition a first radio frequency signal of a first frequency, a plurality of second radio frequency signal conditioning circuits configured to condition a plurality of second radio frequency signals of a second frequency that is greater than the first frequency, a plurality of switches operable in a first mode and a second mode, and an antenna array of including a plurality of antenna elements interconnect by the plurality of switches. The antenna array is operable to handle the first radio frequency signal in the first mode, and to handle the plurality of second radio frequency signals in the second mode.
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公开(公告)号：US20240056035A1
公开(公告)日：2024-02-15
申请号：US18362232
申请日：2023-07-31
CPC分类号： H03F1/32 , H03F3/245 , H03F2200/451
摘要： Apparatus and methods for amplifier linearization are disclosed. In certain embodiments, an RF amplifier includes an RF input terminal that receives an RF input signal, an RF output terminal that provides an RF output signal, a gallium nitride field-effect transistor (GaN FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaN FET amplifies the RF input signal. The RF amplifier further includes a gallium arsenide field-effect transistor (GaAs FET) having a gate connected to the RF input terminal and a drain connected to the RF output terminal. The GaAs FET is operable to linearize the GaN FET.
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公开(公告)号：US11848713B2
公开(公告)日：2023-12-19
申请号：US18174935
申请日：2023-02-27
发明人： Florinel G. Balteanu , Yu Zhu , Paul T. DiCarlo
IPC分类号： H04B17/12 , H04B17/21 , H04B17/14 , H04B17/327 , H04B17/364
CPC分类号： H04B17/12 , H04B17/14 , H04B17/21 , H04B17/327 , H04B17/364
摘要： Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal that is substantially triangular along an envelope path, and by providing an RF signal to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.
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公开(公告)号：US20230283388A1
公开(公告)日：2023-09-07
申请号：US18174935
申请日：2023-02-27
发明人： Florinel G. Balteanu , Yu Zhu , Paul T. DiCarlo
IPC分类号： H04B17/12 , H04B17/21 , H04B17/14 , H04B17/327 , H04B17/364
CPC分类号： H04B17/12 , H04B17/14 , H04B17/21 , H04B17/327 , H04B17/364
摘要： Apparatus and methods for envelope alignment calibration in radio frequency (RF) systems are provided. In certain embodiments, calibration is performed by providing an envelope signal that is substantially triangular along an envelope path, and by providing an RF signal to a power amplifier along an RF signal path. Additionally, an output of the power amplifier is observed to generate an observation signal using an observation receiver. The observation signal includes a first peak and a second peak, and a delay between the envelope signal and the RF signal is controlled based on relative size of the peaks of the observation signal to one another.
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公开(公告)号：US20230238385A1
公开(公告)日：2023-07-27
申请号：US18156661
申请日：2023-01-19
CPC分类号： H01L27/1203 , H01L23/66 , H01L21/84 , H01L2223/6677
摘要： Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.
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公开(公告)号：US20230084412A1
公开(公告)日：2023-03-16
申请号：US17889325
申请日：2022-08-16
发明人： Hailing Wang , Dylan Charles Bartle , Hanching Fuh , Jerod F. Mason , David Scott Whitefield , Paul T. DiCarlo
摘要： Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
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公开(公告)号：US20220329270A1
公开(公告)日：2022-10-13
申请号：US17658231
申请日：2022-04-06
摘要： Apparatus and methods for diplexing by antenna structure are provided. In certain embodiments, a mobile device includes a front end system and an antenna structure. The front end system includes a first signal conditioning circuit configured to condition a first radio frequency signal of a first frequency, and a second signal conditioning circuit configured to condition a second radio frequency signal of a second frequency that is lower than the first frequency. The antenna structure is configured to diplex the first radio frequency signal and the second radio frequency signal, and includes a first antenna configured to handle the first radio frequency signal and a second antenna electromagnetically coupled to the first antenna and configured to handle the second radio frequency signal.
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公开(公告)号：US11418185B2
公开(公告)日：2022-08-16
申请号：US17374881
申请日：2021-07-13
发明人： Hailing Wang , Dylan Charles Bartle , Hanching Fuh , Jerod F. Mason , David Scott Whitefield , Paul T. DiCarlo
摘要： Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
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公开(公告)号：US20210083732A1
公开(公告)日：2021-03-18
申请号：US17035406
申请日：2020-09-28
IPC分类号： H04B7/0413 , H04B7/0404 , H04L25/06
摘要： Apparatus and methods for multi-antenna communications are provided. In certain embodiments, a communication system includes an antenna array including a plurality of antenna elements, and a plurality of RF circuit channels each coupled to a corresponding one of the antenna elements. The plurality of RF circuit channels generate two or more analog baseband signals in response to the antenna array receiving a radio wave. The communication system further includes a controllable amplification and combining circuit that generates two or more amplified analog baseband signals based on amplifying each of the two or more analog baseband signals with a separately controllable gain, and that combines the two or more amplified analog baseband signals to generate a combined analog baseband signal.
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公开(公告)号：US20210075417A1
公开(公告)日：2021-03-11
申请号：US17009060
申请日：2020-09-01
发明人： Hailing Wang , Dylan Charles Bartle , Hanching Fuh , Jerod F. Mason , David Scott Whitefield , Paul T. DiCarlo
摘要： Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
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