公开(公告)号：US20050108479A1

公开(公告)日：2005-05-19

申请号：US10704286

申请日：2003-11-06

申请人： Sridhar Lakshmanamurthy ,  Wilson Liao ,  Prashant Chandra ,  Jeen-Yuan Miin ,  Yim Pun

发明人： Sridhar Lakshmanamurthy ,  Wilson Liao ,  Prashant Chandra ,  Jeen-Yuan Miin ,  Yim Pun

IPC分类号： G06F12/08 ,  G06F13/28

CPC分类号： G06F12/0811

摘要： In general, in one aspect, the disclosure describes a processor that includes a memory to store at least a portion of instructions of at least one program and multiple packet engines that include an engine instruction cache to store a subset of the at least one program. The processor also includes circuitry coupled to the packet engines and the memory to receive requests from the multiple engines for subsets of the at least one portion of the at least one set of instructions.

摘要翻译： 通常，在一个方面，本发明描述了一种处理器，其包括存储器，用于存储至少一个程序和多个分组引擎的指令的至少一部分，所述指令包括引擎指令高速缓存以存储所述至少一个程序的子集。 处理器还包括耦合到分组引擎和存储器的电路，用于接收来自多个引擎的针对至少一组指令的至少一部分的子集的请求。

公开(公告)号：US07698498B2

公开(公告)日：2010-04-13

申请号：US11321273

申请日：2005-12-29

申请人： Sridhar Lakshmanamurthy ,  Dharmin Y. Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

发明人： Sridhar Lakshmanamurthy ,  Dharmin Y. Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

IPC分类号： G06F12/00 ,  G06F13/14

CPC分类号： G06F13/28 ,  G06F13/1631 ,  G06F13/1673

摘要： In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

摘要翻译： 在一些实施例中，公开了一种存储器控制器，其包括用于接收命令和地址的至少一个命令/地址输入缓冲器。 地址指定存储体和存储体内的位置。 耦合到至少一个命令/地址输入缓冲器的仲裁器合并来自至少一个命令/地址输入缓冲器的命令和地址，并根据指定的地址对命令和地址进行排序。 耦合到仲裁器并与存储器组相关联的多个存储体缓冲器接收它们相关存储体的命令和地址。 基于对来自存储体缓冲器的至少一个命令和地址的检查，耦合到多个存储体缓冲器的调度器分组命令和地址。 其他实施例在此另外公开。

公开(公告)号：US07653069B2

公开(公告)日：2010-01-26

申请号：US11322993

申请日：2005-12-30

申请人： Sridhar Lakshmanamurthy ,  Hugh Wilkinson

发明人： Sridhar Lakshmanamurthy ,  Hugh Wilkinson

IPC分类号： H04L12/28 ,  H04L12/50

CPC分类号： H04L47/621 ,  H04L47/50 ,  H04L47/60 ,  H04L47/6215

摘要： In a node to forward data on a switch fabric, a method that includes scheduling the forwarding of data associated with one of a plurality of traffic classes. The data is to be transmitted through one of a plurality of ports coupled to the switch fabric, each port to be associated with a queue to store data to be forwarded from that port. The scheduling is to include a two stage arbitration scheme. The first stage is to select one queue associated for each traffic class. The second stage is to select one queue from among the queues selected for each traffic class selected in the first stage.

摘要翻译： 在用于在交换结构上转发数据的节点中，包括调度与多个业务类中的一个相关联的数据的转发的方法。 数据将通过耦合到交换结构的多个端口中的一个发送，每个端口与队列相关联，以存储要从该端口转发的数据。 调度是包括两阶段仲裁方案。 第一阶段是选择与每个流量类相关联的一个队列。 第二阶段是从在第一阶段中选择的每个流量类别选择的队列中选择一个队列。

公开(公告)号：US20090089546A1

公开(公告)日：2009-04-02

申请号：US12313247

申请日：2008-11-18

申请人： Sridhar Lakshmanamurthy ,  Wilson Y. Liao ,  Prashant R. Chandra ,  Jeen-Yuan Miin ,  Yim Pun

发明人： Sridhar Lakshmanamurthy ,  Wilson Y. Liao ,  Prashant R. Chandra ,  Jeen-Yuan Miin ,  Yim Pun

IPC分类号： G06F9/30

CPC分类号： G06F12/0811 ,  G06F12/0842 ,  H04L69/12

摘要： In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

摘要翻译： 一般来说，一方面，本发明描述了一种处理器，其包括指令存储器，用于存储至少一个程序的至少一部分和耦合到共享指令存储器的多个引擎的指令。 引擎提供多个执行线程并且包括指令高速缓存以从指令存储器缓存至少一个程序的至少一部分的子集，其中引擎指令高速缓存的不同相应部分分配给引擎的不同相应引擎 线程。

公开(公告)号：US07366865B2

公开(公告)日：2008-04-29

申请号：US10936917

申请日：2004-09-08

申请人： Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

发明人： Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

IPC分类号： G06F12/06 ,  H04N7/16

CPC分类号： G06F12/0804 ,  G06F12/0875

摘要： Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation. The pointer is updated in the third memory area to point to the added entry in the packet queue and the updated pointer in the third memory area is written to the queue descriptor in the second memory area in one write operation.

摘要翻译： 提供了一种方法，系统，网络处理器，网络设备和用于引入分组的分组队列中的入口的入口制品。 当向第一存储器区域添加分组时，将条目写入参考所添加的分组的第二存储器区域中的分组队列。 在一次读取操作中，将指针从第二存储器区域中的队列描述符引用到分组队列的一端到第三存储器区域中。 指针在第三存储器区域被更新以指向分组队列中的添加的条目，并且在一个写入操作中将第三存储器区域中的更新的指针写入第二存储器区域中的队列描述符。

公开(公告)号：US07251219B2

公开(公告)日：2007-07-31

申请号：US10188081

申请日：2002-07-03

申请人： Sridhar Lakshmanamurthy ,  Lawrence B. Huston ,  Yim Pun ,  Raymond Ng ,  Hugh M. Wilkinson, III ,  Mark B. Rosenbluth ,  David Romano

发明人： Sridhar Lakshmanamurthy ,  Lawrence B. Huston ,  Yim Pun ,  Raymond Ng ,  Hugh M. Wilkinson, III ,  Mark B. Rosenbluth ,  David Romano

IPC分类号： H04B1/44

CPC分类号： H04L49/30 ,  H04L47/10 ,  H04L47/266 ,  H04L47/30 ,  H04L49/254 ,  H04L49/50

摘要： In-band flow control data may be received from a switch fabric at a first network processor. The received in-band flow control data may be transmitted to a second network processor using a flow control bus. The second network processor may determine which receive queues in the switch fabric exceed a predetermined overflow threshold based on the in-band flow control data. The second processor may transmit data to the receive queues in the switch fabric determined not to exceed the predetermined overflow threshold.

摘要翻译： 可以在第一网络处理器处从交换结构接收带内流控制数据。 接收到的带内流控制数据可以使用流控制总线发送到第二网络处理器。 第二网络处理器可以基于带内流控制数据来确定交换结构中的接收队列超过预定的溢出阈值。 第二处理器可以将数据发送到被确定为不超过预定溢出阈值的交换结构中的接收队列。

公开(公告)号：US20070156946A1

公开(公告)日：2007-07-05

申请号：US11321273

申请日：2005-12-29

申请人： Sridhar Lakshmanamurthy ,  Dharmin Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

发明人： Sridhar Lakshmanamurthy ,  Dharmin Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

IPC分类号： G06F12/06 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F13/1631 ,  G06F13/1673

摘要： In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

摘要翻译： 在一些实施例中，公开了一种存储器控制器，其包括用于接收命令和地址的至少一个命令/地址输入缓冲器。 地址指定存储体和存储体内的位置耦合到至少一个命令/地址输入缓冲器的仲裁器从至少一个命令/地址输入缓冲器合并命令和地址，并根据 指定的地址。 耦合到仲裁器并与存储器组相关联的多个存储体缓冲器接收它们相关存储体的命令和地址。 基于对来自存储体缓冲器的至少一个命令和地址的检查，耦合到多个存储体缓冲器的调度器分组命令和地址。 其他实施例在此另外公开。

公开(公告)号：US20060221980A1

公开(公告)日：2006-10-05

申请号：US11097067

申请日：2005-03-31

申请人： Bijoy Bose ,  Sridhar Lakshmanamurthy ,  Mark Rosenbluth ,  Irwin Vaz ,  Suri Medapati ,  Edwin O'Yang

发明人： Bijoy Bose ,  Sridhar Lakshmanamurthy ,  Mark Rosenbluth ,  Irwin Vaz ,  Suri Medapati ,  Edwin O'Yang

IPC分类号： H04L12/56 ,  H04L12/28 ,  H04L12/66

CPC分类号： H04L49/101 ,  H04L49/254

摘要： A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage. Another embodiment employs a complementary rotating priority arbitration scheme at the second stage.

公开(公告)号：US20060036817A1

公开(公告)日：2006-02-16

申请号：US10915751

申请日：2004-08-10

申请人： Alpesh Oza ,  Rohit Verma ,  Sridhar Lakshmanamurthy

发明人： Alpesh Oza ,  Rohit Verma ,  Sridhar Lakshmanamurthy

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/3816 ,  G06F9/3834

摘要： Provided are a method and system for handling unaligned writes in a memory controller. A first write request to a memory device in a queue is processed. The first write request is sent to a read modify write (RMW) engine in response to determining that the first write request is unaligned with respect to a first memory location in the memory device. A second write request that is aligned with respect to a second memory location in the memory device is processed. A determination is made of whether there is one write request pending in the RMW engine to the second memory location. The second write request is executed in response to determining that there is no write request pending in the RMW engine.

摘要翻译： 提供了一种用于在存储器控制器中处理未对齐写入的方法和系统。 对队列中的存储器件的第一次写入请求被处理。 响应于确定第一写请求相对于存储器设备中的第一存储器位置未对准，第一写请求被发送到读修改写（RMW）引擎。 处理与存储器件中的第二存储器位置对准的第二写入请求。 确定RMW引擎中是否有一个写入请求挂起到第二个内存位置。 响应于确定在RMW引擎中没有挂起的请求而执行第二写请求。

公开(公告)号：US20050226235A1

公开(公告)日：2005-10-13

申请号：US10822034

申请日：2004-04-08

申请人： Alok Kumar ,  Michael Kounavis ,  Raj Yavatkar ,  Prashant Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Harrick Vin

发明人： Alok Kumar ,  Michael Kounavis ,  Raj Yavatkar ,  Prashant Chandra ,  Sridhar Lakshmanamurthy ,  Chen-Chi Kuo ,  Harrick Vin

IPC分类号： H04L12/56 ,  H04L29/06 ,  H04Q11/00

CPC分类号： H04L47/10 ,  H04L29/06 ,  H04L47/2441 ,  H04L63/0236 ,  H04L63/0263 ,  H04L69/22

摘要： A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.

摘要翻译： 一种用于两阶段分组分类的方法和装置。 在可以在软件中实现的第一阶段中，基于分组的网络路径以及可能的协议对分组进行分类。 在可以硬件实现的第二阶段中，基于分组的一个或多个传输级别字段对分组进行分类。 两级分组分类的装置可以包括用于第一阶段代码执行的处理系统，用于执行第二阶段分类的分类电路和存储多个分区的存储器，每个分组包括一个或多个规则。