公开(公告)号：US20140015055A1

公开(公告)日：2014-01-16

申请号：US13545597

申请日：2012-07-10

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC分类号： H01L27/088 ,  H01L21/20

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7851

摘要： A method is disclosed for fabricating an integrated circuit in a replacement-gate process flow utilizing a dummy-gate structure overlying a plurality of fin structures. The method includes removing the dummy-gate structure to form a first void space, depositing a shaper material to fill the first void space, removing a portion of the plurality of fin structures to form a second void space, epitaxially growing a high carrier mobility material to fill the second void space, removing the shaper material to form a third void space, and depositing a replacement metal gate material to fill the third void space.

摘要翻译： 公开了一种利用覆盖多个翅片结构的虚拟栅极结构在替代栅极工艺流程中制造集成电路的方法。 该方法包括去除伪栅极结构以形成第一空隙空间，沉积成形材料以填充第一空隙空间，去除多个翅片结构的一部分以形成第二空隙空间，外延生长高载流子迁移率材料 以填充第二空隙空间，移除整形材料以形成第三空隙空间，以及沉积更换的金属栅极材料以填充第三空隙空间。

公开(公告)号：US20130292774A1

公开(公告)日：2013-11-07

申请号：US13465731

申请日：2012-05-07

申请人： Jan Hoentschel ,  Sven Beyer ,  Oliver Kallensee ,  Stefan Flachowsky

发明人： Jan Hoentschel ,  Sven Beyer ,  Oliver Kallensee ,  Stefan Flachowsky

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/1045 ,  H01L29/41783 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A semiconductor device having raised source and drain regions is formed by forming a gate electrode structure on a semiconductor substrate, forming a first spacer structure laterally to the gate electrode structure, forming a semiconductor layer over an exposed surface of the semiconductor substrate at both sides of the gate electrode structure such that a layer portion is formed which is beveled towards the gate electrode with regard to the exposed surface of the semiconductor substrate, and forming a second spacer structure over the first spacer structure, wherein the second spacer structure covers at least a portion of the beveled layer portion.

摘要翻译： 通过在半导体衬底上形成栅电极结构形成具有凸起的源极和漏极区的半导体器件，在栅电极结构上横向形成第一间隔结构，在半导体衬底的两侧的暴露表面上形成半导体层 所述栅电极结构使得形成相对于所述半导体衬底的暴露表面朝向所述栅电极倾斜的层部分，以及在所述第一间隔结构上形成第二间隔结构，其中所述第二间隔结构覆盖至少一个 斜面层部分的一部分。

公开(公告)号：US08415221B2

公开(公告)日：2013-04-09

申请号：US13015239

申请日：2011-01-27

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One method for fabricating a semiconductor device structure involves the steps of forming a gate structure overlying the semiconductor substrate, forming recesses in the semiconductor substrate about the gate structure, forming a stress-inducing semiconductor material in the recesses, and forming a silicon material in the recesses overlying the stress-inducing semiconductor material. In an exemplary embodiment, the silicon material formed in the recesses is epitaxially-grown on the stress-inducing semiconductor material.

摘要翻译： 提供了具有硅封装应力区域的半导体器件结构的装置和相关的制造方法。 一种用于制造半导体器件结构的方法包括以下步骤：形成覆盖半导体衬底的栅极结构，在半导体衬底周围形成围绕栅极结构的凹槽，在凹槽中形成应力诱导半导体材料，并在其中形成硅材料 覆盖应力诱导半导体材料的凹部。 在示例性实施例中，形成在凹槽中的硅材料在应力诱导半导体材料上外延生长。

公开(公告)号：US20130069111A1

公开(公告)日：2013-03-21

申请号：US13235211

申请日：2011-09-16

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7848

摘要： Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

摘要翻译： 提供应变半导体器件的实施例，如制造这种应变半导体器件的方法的实施例。 在一个实施例中，该方法包括提供部分制造的半导体器件，其包括具有源极侧和漏极侧的半导体衬底，形成在半导体衬底上的栅极叠层以及形成在栅叠层下方的半导体衬底内的沟道区，以及 从半导体衬底的源极侧向漏极侧延伸。 在半导体衬底的源极侧和漏极侧仅产生空腔，并且在空腔内形成应变诱导材料，以在半导体衬底内形成不对称的异质结结构。

公开(公告)号：US09093554B2

公开(公告)日：2015-07-28

申请号：US13470454

申请日：2012-05-14

申请人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

IPC分类号： H01L21/00 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

摘要： In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.

摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬里层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。

公开(公告)号：US08647951B2

公开(公告)日：2014-02-11

申请号：US13216862

申请日：2011-08-24

申请人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC分类号： H01L21/38 ,  H01L21/336

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/32155 ,  H01L21/823857

摘要： Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.

摘要翻译： 通常，本公开涉及通过注入氢或含氢簇来改善栅极绝缘层和衬底之间的界面来制造半导体器件的各种方法。 本文公开的一种说明性方法包括在衬底上形成栅极绝缘层，在栅极绝缘材料上方形成栅极材料层，并用含有氢或含氢化合物的材料进行离子注入工艺以引入氢或氢 邻近于栅极绝缘层和所述衬底之间的界面，其中所注入的氢或含氢化合物的浓度为至少1e 10离子/ cm 2。

公开(公告)号：US20140015060A1

公开(公告)日：2014-01-16

申请号：US13545624

申请日：2012-07-10

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/31 ,  H01L27/092

CPC分类号： H01L21/823807 ,  H01L27/092

摘要： A method for fabricating a stress enhanced CMOS circuit includes forming a first plurality of MOS transistors at a first pitch and forming a second plurality of MOS transistors at a second pitch. The second pitch is larger than the first pitch. The method further includes depositing a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner deposited in the fabrication of the stress enhanced CMOS circuit. A stress enhanced CMOS circuit includes a first plurality of MOS transistors formed at a first pitch and a second plurality of MOS transistors formed at a second pitch. The second pitch is larger than the first pitch. The circuit further includes a single stress liner overlying the first and second plurality of MOS transistors. The single stress liner is the only stress liner formed on the stress enhanced CMOS circuit.

摘要翻译： 制造应力增强型CMOS电路的方法包括以第一间距形成第一多个MOS晶体管，并以第二间距形成第二多个MOS晶体管。 第二间距大于第一间距。 该方法还包括沉积覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是沉积在应力增强CMOS电路制造中的唯一应力衬垫。 应力增强型CMOS电路包括以第一间距形成的第一多个MOS晶体管和以第二间距形成的第二多个MOS晶体管。 第二间距大于第一间距。 电路还包括覆盖第一和第二多个MOS晶体管的单个应力衬垫。 单应力衬垫是在应力增强CMOS电路上形成的唯一应力衬垫。

公开(公告)号：US08471342B1

公开(公告)日：2013-06-25

申请号：US13315939

申请日：2011-12-09

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/70

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

摘要： Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.

摘要翻译： 与集成电路的实施例一样，提供了集成电路的制造方法的实施例。 在一个实施例中，该方法包括提供具有n-有源区和p-有源区的应变衬底，将空腔蚀刻到n-有源区和p-有源区中的一个中，将松弛缓冲层嵌入腔内 在松弛的缓冲层上形成应变材料体，其应变取向与应变基板的应变方向相反，并且分别在n-活性区域和p活性区域上制造n型和t型晶体管。 n型晶体管的沟道在应变衬底和应变材料体之一内延伸，而p型晶体管的沟道在应变衬底和应变材料体的另一个内延伸。

公开(公告)号：US20130157421A1

公开(公告)日：2013-06-20

申请号：US13331951

申请日：2011-12-20

申请人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823425

摘要： Embodiments of a method for fabricating an integrated circuit are provided. In one embodiment, the method includes producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, and a gate stack over the channel region. At least one raised electrically-conductive structure is formed over at least one of the S/D regions and separated from the gate stack by a lateral gap. The raised electrically-conductive structure is then back-etched to increase the width of the lateral gap and reduce the parasitic fringing capacitance between the raised electrically-conductive structure and the gate stack during operation of the completed semiconductor device.

摘要翻译： 提供了一种用于制造集成电路的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件，其包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域和沟道区域上的栅极堆叠。 在至少一个S / D区域上形成至少一个凸起的导电结构，并且通过侧向间隙与栅极堆叠分离。 然后，升高的导电结构被反蚀刻以增加横向间隙的宽度，并且在完成的半导体器件的操作期间减小凸起的导电结构和栅极堆叠之间的寄生边缘电容。

公开(公告)号：US20130146976A1

公开(公告)日：2013-06-13

申请号：US13315939

申请日：2011-12-09

申请人： Stefan Flachowsky ,  Jan Hoentschel

发明人： Stefan Flachowsky ,  Jan Hoentschel

IPC分类号： H01L21/8238 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

摘要： Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.

摘要翻译： 与集成电路的实施例一样，提供了集成电路的制造方法的实施例。 在一个实施例中，该方法包括提供具有n-有源区和p-有源区的应变衬底，将空腔蚀刻到n-有源区和p-有源区中的一个中，将松弛缓冲层嵌入腔内 在松弛的缓冲层上形成应变材料体，其应变取向与应变基板的应变方向相反，并且分别在n-活性区域和p活性区域上制造n型和t型晶体管。 n型晶体管的沟道在应变衬底和应变材料体之一内延伸，而p型晶体管的沟道在应变衬底和应变材料体的另一个内延伸。