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    METHOD AND APPARATUS FOR IMPROVING THE EFFICIENCY OF INTERRUPT DELIVERY AT RUNTIME IN A NETWORK SYSTEM
    71.
    发明申请
    METHOD AND APPARATUS FOR IMPROVING THE EFFICIENCY OF INTERRUPT DELIVERY AT RUNTIME IN A NETWORK SYSTEM 有权
    提高网络系统运行中断传输效率的方法与装置

    公开(公告)号：US20130173895A1

    公开(公告)日：2013-07-04

    申请号：US13657991

    申请日：2012-10-23

    申请人： Yadong Li ,  Sujoy Sen

    发明人： Yadong Li ,  Sujoy Sen

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F13/24 ,  H04L49/90

    摘要： Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information.

    摘要翻译： 应用程序/线程的处理器亲和性可能用于在运行时将由应用程序/线程引起的中断传递到最佳处理器。 发送中断的处理器可以运行目标应用程序/线程，也可以位于与运行目标应用程序/线程的处理器相同的套接字中。 应用/线程的处理器亲和性可以在运行时被推下到网络设备，芯片组，存储器控制中枢（“MCH”）或输入/输出集线器（“IOH”），这将有利于 中断使用该亲和度信息。

    Method, device, and system for seamless migration of a virtual machine between platforms with different I/O hardware
    74.
    发明授权
    Method, device, and system for seamless migration of a virtual machine between platforms with different I/O hardware 有权
    用于在具有不同I / O硬件的平台之间无缝迁移虚拟机的方法，设备和系统

    公开(公告)号：US08065677B2

    公开(公告)日：2011-11-22

    申请号：US12056136

    申请日：2008-03-26

    申请人： Sujoy Sen ,  Gregory D. Cummings

    发明人： Sujoy Sen ,  Gregory D. Cummings

    IPC分类号： G06F9/455

    CPC分类号： G06F9/4856 ,  G06F9/5077

    摘要： A method, apparatus, system, and computer readable medium are disclosed. In one embodiment the method includes detecting a virtual machine (VM) attempting to communicate with a device coupled to a computer system using a first software plug-in interface that is incompatible with the device. The method continues by temporarily removing the VM from controlling system. Then the first software plug-in interface in the VM is replaced with a second software plug-in interface, which is compatible with the device, without the knowledge of the VM. Then control is returned to the VM and the VM is allowed to resume the communication attempt with the device using the second software plug-in interface.

    摘要翻译： 公开了一种方法，装置，系统和计算机可读介质。 在一个实施例中，该方法包括：使用与设备不兼容的第一软件插件接口来检测尝试与耦合到计算机系统的设备进行通信的虚拟机（VM）。 该方法通过从控制系统临时移除VM来继续。 然后，虚拟机中的第一个软件插件接口被替换为与设备兼容的第二个软件插件接口，而不知道VM。 然后将控制返回给VM，并允许VM使用第二个软件插件接口恢复与设备的通信尝试。

    Packet coalescing
    76.
    发明授权
    Packet coalescing 有权
    分组聚合

    公开(公告)号：US07620071B2

    公开(公告)日：2009-11-17

    申请号：US10991239

    申请日：2004-11-16

    申请人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

    发明人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

    IPC分类号： H04J3/24

    CPC分类号： H04L45/74 ,  H04L49/20 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166

    摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    摘要翻译： 一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段 协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。 该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷 。 该方法还包括产生导致因特网协议分组的接收处理的信号。

    I/O hub resident cache line monitor and device register update
    77.
    发明授权
    I/O hub resident cache line monitor and device register update 有权
    I / O集线器驻留高速缓存行监视器和设备寄存器更新

    公开(公告)号：US07581042B2

    公开(公告)日：2009-08-25

    申请号：US11026928

    申请日：2004-12-29

    申请人： Dave Minturn ,  James B. Crossland ,  Sujoy Sen ,  Greg Cummings

    发明人： Dave Minturn ,  James B. Crossland ,  Sujoy Sen ,  Greg Cummings

    IPC分类号： G06F3/00

    CPC分类号： G06F12/0875 ,  G06F12/0862

    摘要： The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.

    摘要翻译： 本文描述的装置和方法用于实现对I / O设备寄存器的可高速缓存写入。 可能存在于控制器集线器中的高速缓存监视器监视对微处理器中的高速缓存行的访问。 高速缓存监视器还将微处理器中的高速缓存行与I / O设备寄存器相关联。 当检测到对某些高速缓存行的访问时，高速缓存监视器可操作以接收高速缓存行的内容并将这些内容写入相关联的I / O设备寄存器。 因此，微处理器可以写入高速缓存线，而不是直接对I / O设备寄存器进行不可写的写操作。

    Integrated circuit capable of marker stripping
    78.
    发明授权
    Integrated circuit capable of marker stripping 有权
    能够进行标记剥离的集成电路

    公开(公告)号：US07433975B2

    公开(公告)日：2008-10-07

    申请号：US11088474

    申请日：2005-03-24

    申请人： Steven R King ,  Ronald Dammann ,  Sujoy Sen

    发明人： Steven R King ,  Ronald Dammann ,  Sujoy Sen

    IPC分类号： G06F13/28 ,  G06F3/00

    CPC分类号： H04L49/9063 ,  H04L49/90

    摘要： A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

    摘要翻译： 一种方法，系统，计算机程序产品和扩展卡，其能够：在源存储器设备内定义初始源地址。 执行初始数据读取操作以从源存储器件检索第一X字节数据部分。 初始数据读取操作从初始源地址开始。 初始源地址增加Y字节，以定义源存储器件中的次级源地址，使得Y大于X.

    Chipset feature detection and configuration by an I/O device
    79.
    发明授权
    Chipset feature detection and configuration by an I/O device 有权
    芯片组特征检测和I / O设备配置

    公开(公告)号：US07363393B2

    公开(公告)日：2008-04-22

    申请号：US10750060

    申请日：2003-12-30

    申请人： William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    发明人： William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4027

    摘要： Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

    摘要翻译： 用于第一设备的第二设备查询第二设备内的硬件特征的可用性的装置和方法，以及第二设备接收和分析查询以确定是否响应，取决于所寻求的硬件特征的版本 ，识别供应商等的代码，并且如果确定作出回复，则响应提供硬件特征的可用性的指示和/或可以访问硬件特征的地址。

    Integrated circuit capable of marker stripping
    80.
    发明申请
    Integrated circuit capable of marker stripping 有权
    能够进行标记剥离的集成电路

    公开(公告)号：US20060218308A1

    公开(公告)日：2006-09-28

    申请号：US11088474

    申请日：2005-03-24

    申请人： Steven King ,  Ronald Dammann ,  Sujoy Sen

    发明人： Steven King ,  Ronald Dammann ,  Sujoy Sen

    IPC分类号： G06F3/00

    CPC分类号： H04L49/9063 ,  H04L49/90

    摘要： A method, system, computer program product, and expansion card capable of: defining an initial source address within a source memory device. An initial data read operation is performed to retrieve a first X-byte data portion from the source memory device. The initial data read operation begins at the initial source address. The initial source address is incremented by Y bytes to define a secondary source address within the source memory device, such that Y is greater than X.

    摘要翻译： 一种方法，系统，计算机程序产品和扩展卡，其能够：在源存储器设备内定义初始源地址。 执行初始数据读取操作以从源存储器件检索第一X字节数据部分。 初始数据读取操作从初始源地址开始。 初始源地址增加Y字节，以定义源存储器件中的次级源地址，使得Y大于X.