公开(公告)号：US11581250B2

公开(公告)日：2023-02-14

申请号：US17218285

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

公开(公告)号：US20220359410A1

公开(公告)日：2022-11-10

申请号：US17873387

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US20220328392A1

公开(公告)日：2022-10-13

申请号：US17808827

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

公开(公告)号：US11296065B2

公开(公告)日：2022-04-05

申请号：US16901682

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Techi Wong ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Meng-Wei Chou

IPC: H01L23/02 ,  H01L25/18 ,  H01L27/01 ,  H01L23/31 ,  H01L25/065 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538

Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.

公开(公告)号：US11282759B2

公开(公告)日：2022-03-22

申请号：US16816455

申请日：2020-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng ,  Shuo-Mao Chen

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, a first semiconductor device, a second semiconductor device, and a protective layer. The interposer substrate is disposed over the package substrate. The first semiconductor device and the second semiconductor device are disposed over the interposer substrate, wherein the first semiconductor device and the second semiconductor device are different types of electronic devices. The protective layer is formed over the interposer substrate to surround the first semiconductor device and the second semiconductor device. The second semiconductor device is exposed from the protective layer and the first semiconductor device is not exposed from the protective layer.

公开(公告)号：US11270975B2

公开(公告)日：2022-03-08

申请号：US16934861

申请日：2020-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

公开(公告)号：US11239194B2

公开(公告)日：2022-02-01

申请号：US16750071

申请日：2020-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/29 ,  H01L21/78

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The second chip includes a second substrate and a second conductive pad over the second substrate, and the second conductive pad is between the second substrate and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the wiring layers.

公开(公告)号：US11107801B2

公开(公告)日：2021-08-31

申请号：US16233653

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Lin ,  Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Chia-Hsiang Lin

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L21/32 ,  H01L25/00 ,  G03F7/20 ,  H01L21/033

Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.

公开(公告)号：US10714463B2

公开(公告)日：2020-07-14

申请号：US16693337

申请日：2019-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Cheng-Yi Hong ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Shu-Shen Yeh ,  Kuang-Chun Lee

IPC: H01L23/053 ,  H01L23/12 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L25/00 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L23/538 ,  H01L23/373

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

公开(公告)号：US10283474B2

公开(公告)日：2019-05-07

申请号：US15708456

申请日：2017-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/29 ,  H01L23/31 ,  H01L21/78

Abstract: A method for forming a chip package structure is provided. The method includes forming a first dielectric layer over a carrier substrate. The first dielectric layer is a continuous dielectric layer and has openings. The method includes forming a first wiring layer over the first dielectric layer and in the openings. The first dielectric layer and the first wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface. The method includes disposing a first chip and a first conductive bump over the first surface. The method includes forming a first molding layer over the first surface. The method includes removing the carrier substrate. The method includes disposing a second chip and a second conductive bump over the second surface. The method includes forming a second molding layer over the second surface.