公开(公告)号：US10985022B2

公开(公告)日：2021-04-20

申请号：US16203744

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Chun-I Wu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/3115

Abstract: Examples of a method of forming an integrated circuit device with an interfacial layer disposed between a channel region and a gate dielectric are provided herein. In some examples, the method includes receiving a workpiece having a substrate and a fin having a channel region disposed on the substrate. An interfacial layer is formed on the channel region of the fin, and a gate dielectric layer is formed on the interfacial layer. A first capping layer is formed on the gate dielectric layer, and a second capping layer is formed on the first capping layer. An annealing process is performed on the workpiece configured to cause a first material to diffuse from the first capping layer into the gate dielectric layer. The forming of the first and second capping layers and the annealing process may be performed in the same chamber of a fabrication tool.

公开(公告)号：US10971402B2

公开(公告)日：2021-04-06

申请号：US16443016

申请日：2019-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  I-Ming Chang ,  Hsiang-Pi Chang ,  Yu-Wei Lu ,  Ziwei Fang ,  Huang-Lin Chao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L21/02

Abstract: A method includes providing a channel region and growing an oxide layer on the channel region. Growing the oxide layer includes introducing a first source gas providing oxygen and introducing a second source gas providing hydrogen. The second source gas being different than the first source gas. The growing the oxide layer is grown by bonding the oxygen to a semiconductor element of the channel region to form the oxide layer and bonding the hydrogen to the semiconductor element of the channel region to form a semiconductor hydride byproduct. A gate dielectric layer and electrode can be formed over the oxide layer.

公开(公告)号：US10964792B1

公开(公告)日：2021-03-30

申请号：US16692127

申请日：2019-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/41 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20210057581A1

公开(公告)日：2021-02-25

申请号：US16549245

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US10818768B1

公开(公告)日：2020-10-27

申请号：US16427102

申请日：2019-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/285

Abstract: A method for forming a semiconductor structure is provided. The method includes patterning a semiconductor substrate to form a semiconductor fin, forming a source/drain structure on the semiconductor fin, forming a gate electrode layer across the semiconductor fin, forming a first halogen-containing metal cap layer on the gate electrode layer, forming a contact structure on the source/drain structure and connected to the source/drain structure, and forming a second halogen-containing metal cap layer on the contact structure. The first halogen-containing metal cap layer and the second halogen-containing metal cap layer include different halogens.

公开(公告)号：US10770563B2

公开(公告)日：2020-09-08

申请号：US16363109

申请日：2019-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same are provided. In one embodiment, the semiconductor device includes a semiconductor substrate, a plurality of channel regions including first, second, and third p-type channel regions as well as first, second, and third n-type channel regions, and a plurality of gate structures. The plurality of gate structures includes an interfacial layer (IL) disposed over the plurality of channel regions, a first high-k (HK) dielectric layer disposed over the first p-type channel region and the first n-type channel region, a second high-k dielectric layer disposed over the first n-type channel region, the second n-type channel region, the first p-type channel region, and the second p-type channel region; and a third high-k dielectric layer disposed over the plurality of channel regions. The first, second and third high-k dielectric layers are different from one another.

公开(公告)号：US20200279949A1

公开(公告)日：2020-09-03

申请号：US16877505

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66

Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.

公开(公告)号：US20200279846A1

公开(公告)日：2020-09-03

申请号：US16852564

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L29/06

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US10707320B2

公开(公告)日：2020-07-07

申请号：US16218151

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Kai Tak Lam ,  Sai-Hooi Yeong ,  Chi On Chui ,  Ziwei Fang

IPC: H01L21/00 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L21/768

Abstract: A method of forming a semiconductor device includes forming a hafnium-containing layer over a semiconductor layer, simultaneously performing a thermal annealing process and applying an electrical field to the hafnium-containing layer to form a ferroelectric hafnium-containing layer, and forming a gate electrode over the ferroelectric hafnium-containing layer.

公开(公告)号：US10573749B2

公开(公告)日：2020-02-25

申请号：US15054089

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Shiu-Ko JangJian ,  Kei-Wei Chen ,  Huai-Tei Yang ,  Ying-Lang Wang

IPC: H01L27/01 ,  H01L29/78 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.