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85 条记录 (耗时 0.04 秒)

    Parallel precoder circuit
    71.
    发明授权
    Parallel precoder circuit 有权
    并行预编码电路

    公开(公告)号：US07428692B2

    公开(公告)日：2008-09-23

    申请号：US11349248

    申请日：2006-02-08

    申请人： Yoshiaki Konishi ,  Kazuo Kubo

    发明人： Yoshiaki Konishi ,  Kazuo Kubo

    IPC分类号： G11C29/00

    CPC分类号： H04B10/5055 ,  H04B10/505 ,  H04B10/5053 ,  H04B10/5561 ,  H04L25/497 ,  H04L27/2071 ,  H04L27/2096

    摘要： A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2≦n. Output sets of differential encoding operation circuits each of which having a largest column number from among differential encoding operation circuits disposed in first row to (n−1)th row become first-row to (n−1)th-row parallel outputs information series, and an output set of an nth-row delay circuit becomes nth-row parallel output information series.

    摘要翻译： 并行预编码器电路对n行并行输入信息序列执行差分编码操作，并且输出n行并行输出信息序列，其中2 <= n。 从布置在第一行至第（n-1）行的差分编码运算电路中，每个具有最大列数的差分编码运算电路的输出组成为第一行至第（n-1）行并行输出信息序列 并且第n行延迟电路的输出组成为第n行并行输出信息序列。

    Optical reception apparatus
    73.
    发明授权
    Optical reception apparatus 有权
    光接收装置

    公开(公告)号：US07239673B2

    公开(公告)日：2007-07-03

    申请号：US10416550

    申请日：2002-09-12

    申请人： Kazushige Sawada ,  Kazuo Kubo ,  Takashi Mizuochi ,  Hideo Yoshida ,  Hachiro Fujita ,  Katsuhiro Shimizu ,  Junichi Abe

    发明人： Kazushige Sawada ,  Kazuo Kubo ,  Takashi Mizuochi ,  Hideo Yoshida ,  Hachiro Fujita ,  Katsuhiro Shimizu ,  Junichi Abe

    IPC分类号： H03K9/00 ,  H04L27/00

    CPC分类号： H03M13/6325 ,  G11B20/1833 ,  H04B10/695 ,  H04L1/004 ,  H04L25/063 ,  H04L25/067

    摘要： An optical receiver includes a soft-decision deciding unit (7) for deciding an electric received signal according to a plurality of decision levels to output a multivalued decision signal, a demultiplexing unit (5) for serial-to-parallel converting the multivalued decision signal to output a multivalued parallel signal, a soft-decision error correction decoding unit (8) for correcting the multivalued parallel signal based on reliability information to output an error-corrected parallel received signal and decision results indicating the decision of the electric received signal according to the plurality of decision levels, a probability density distribution estimation unit (9) for estimating probability density distributions based on distributions of the decision results, and a decision level control unit (10) for controlling the plurality of decision levels based on the probability density distributions, thereby improving the transmission quality.

    摘要翻译： 一种光接收机包括：软判决决定单元，用于根据多个判决电平决定电接收信号以输出多值判定信号;解复用单元，用于串并转换多值判定信号; 输出多值并行信号;软判决纠错解码单元，用于根据可靠性信息校正多值并行信号，以输出纠错后的并行接收信号;以及判定结果，其指示电接收信号根据 所述多个判定级别，基于所述判定结果的分布来估计概率密度分布的概率密度分布估计单元（9），以及用于基于所述概率密度分布来控制所述多个判定级别的判定级别控制单元（10） ，从而提高传输质​​量。

    FEC frame structuring method and FEC multiplexer
    74.
    发明授权
    FEC frame structuring method and FEC multiplexer 失效
    FEC帧结构方法和FEC多路复用器

    公开(公告)号：US06868514B2

    公开(公告)日：2005-03-15

    申请号：US09890858

    申请日：2000-12-06

    申请人： Kazuo Kubo ,  Hideo Yoshida ,  Hiroshi Ichibangase ,  Hidenori Taga ,  Eiichi Shibano ,  Tadami Yasuda

    发明人： Kazuo Kubo ,  Hideo Yoshida ,  Hiroshi Ichibangase ,  Hidenori Taga ,  Eiichi Shibano ,  Tadami Yasuda

    IPC分类号： H03M13/15 ,  H03M13/27 ,  H03M13/29 ,  H04J3/00 ,  H04L1/00

    CPC分类号： H03M13/2921 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2721 ,  H03M13/6561

    摘要： In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is returned to the original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct errors in the information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit 37.

    摘要翻译： 在FEC帧结构方法和FEC多路复用器中，由第一交织电路32改变信息的顺序，由RS（239,223）编码电路33生成第一纠错码，顺序返回到 通过第一去交织电路34的原始顺序，并且由RS（255,239）编码装置5产生第二纠错码。第二纠错码由RS（255,239）解码电路11解码以校正错误 在信息中，通过第二交错电路35改变信息的顺序，由RS（239,223）解码电路36对第一纠错码进行解码，以校正信息中的残差，并将顺序返回到 通过第二去交织电路37的原始顺序。

    Quinoline derivatives and quinazoline derivatives
    76.
    发明授权
    Quinoline derivatives and quinazoline derivatives 失效
    喹啉衍生物和喹唑啉衍生物

    公开(公告)号：US06797823B1

    公开(公告)日：2004-09-28

    申请号：US09889858

    申请日：2001-07-23

    申请人： Kazuo Kubo ,  Yasunari Fujiwara ,  Toshiyuki Isoe

    发明人： Kazuo Kubo ,  Yasunari Fujiwara ,  Toshiyuki Isoe

    IPC分类号： C07D23988

    CPC分类号： C07D215/233 ,  C07D231/12 ,  C07D233/56 ,  C07D239/88 ,  C07D249/08 ,  C07D401/12 ,  C07D403/12

    摘要： An object of the present invention is to provide compounds which have antitumor activity and do not change cytomorphosis. Disclosed are compounds represented by formula (I) and a pharmaceutically acceptable salts and solvates thereof and pharmaceutical compositions comprising said compounds: wherein X and Z each independently represent CH or N; R1 to R3 represent H, substituted alkoxy, unsubstituted alkoxy or the like; R4 represents H; R5 to R8 represent H, halogen, alkyl, alkoxy, alkylthio, nitro, or amino, provided that R5 to R8 do not simultaneously represent H; R9 and R10 represent H, alkyl, or alkylcarbonyl; and R11 represents alkyl, alkenyl, alkynyl, or aralkyl.

    摘要翻译： 本发明的目的是提供具有抗肿瘤活性并且不改变细胞毒性的化合物。 公开了由式（I）表示的化合物及其药学上可接受的盐和溶剂合物和包含所述化合物的药物组合物：其中X和Z各自独立地表示CH或N; R 1至R 3代表H，取代的烷氧基，未被取代的烷氧基等; R 4表示H; R 5至R 8表示H，卤素，烷基，烷氧基，烷硫基，硝基或氨基，条件是R 5至R 8不同时表示H; R 9和R 10代表H，烷基或烷基羰基; R 11表示烷基，烯基，炔基或芳烷基。

    Process for producing quinolone derivatives
    77.
    发明授权
    Process for producing quinolone derivatives 有权
    制备喹诺酮衍生物的方法

    公开(公告)号：US06187926B1

    公开(公告)日：2001-02-13

    申请号：US09420521

    申请日：1999-10-18

    申请人： Tatsushi Osawa ,  Kazuo Kubo ,  Hideko Murooka ,  Tatsuo Nakajima

    发明人： Tatsushi Osawa ,  Kazuo Kubo ,  Hideko Murooka ,  Tatsuo Nakajima

    IPC分类号： C07D215233

    CPC分类号： C07D215/233

    摘要： The present invention relates to a process for producing a 4-quinolone derivative, comprising allowing an o-aminoacetophenone derivative to react with a formic acid in an aprotic solvent in the presence of a suitable base, and adding a protic solvent to the reaction mixture. This is a simple process for producing 4-quinolone derivatives, applicable to large-scale commercial production.

    摘要翻译： 本发明涉及一种4-喹诺酮衍生物的制备方法，其包括在合适的碱存在下使邻氨基苯乙酮衍生物与非质子溶剂中的甲酸反应，并向反应混合物中加入质子溶剂。 这是生产4-喹诺酮衍生物的简单方法，适用于大规模商业化生产。

    Package-type oil-cooled air compressor
    79.
    发明授权
    Package-type oil-cooled air compressor 失效
    包装式油冷空气压缩机

    公开(公告)号：US5507618A

    公开(公告)日：1996-04-16

    申请号：US418446

    申请日：1995-04-07

    申请人： Kazuo Kubo ,  Koji Akashi ,  Keitaro Ishikawa

    发明人： Kazuo Kubo ,  Koji Akashi ,  Keitaro Ishikawa

    IPC分类号： F04C18/16 ,  F04C23/00 ,  F04C29/04 ,  F04C29/06 ,  F01D25/14

    CPC分类号： F04C29/04 ,  F04C23/00

    摘要： This invention provides a package-type oil-cooled air compressor in which the housing is divided into two chambers, in one of which, a first chamber, are located the compressor unit, motor used to drive the compressor unit, air intake filter and intake regulator valve connected to the compressor unit, and in the other of which, a second chamber, are located the oil cooler and sirocco fan. An air duct connects the two chambers. Air outlets are formed in each of the chambers and an air inlet is formed in the second chamber. Air is introduced through the rotation of the sirocco fan into the second chamber via the air inlet. A portion of this air is directed into the first chamber via the air duct where a part is used to supply the compressor unit and the remainder flows over the components located in the first chamber to cool them and leaves via the outlet formed in the first chamber. The air that is not directed into the first chamber via the duct leaves the outlet formed in the second chamber after flowing over the oil cooler.

    摘要翻译： 本发明提供了一种封装式油冷空气压缩机，其中壳体被分成两个腔室，其中一个腔室中的第一腔室位于压缩机单元，用于驱动压缩机单元的电动机，进气过滤器和进气口 调节阀连接到压缩机单元，而另一个第二室位于油冷却器和西洛克风扇。 空气管道连接两个室。 在每个室中形成空气出口，并且在第二室中形成空气入口。 空气通过空气入口通过西洛可风扇的旋转引入第二室。 该空气的一部分经由空气管道被引导到第一室中，其中一部分用于供应压缩机单元，其余部分流过位于第一室中的部件，以冷却它们并经由形成在第一室中的出口离开 。 通过管道未被引导到第一室中的空气在流过油冷却器之后离开在第二室中形成的出口。

    Frame phase synchronization apparatus and method, and a phase synchronization apparatus of TDM frames
    80.
    发明授权
    Frame phase synchronization apparatus and method, and a phase synchronization apparatus of TDM frames 失效
    帧相位同步装置和方法，以及TDM帧的相位同步装置

    公开(公告)号：US5452305A

    公开(公告)日：1995-09-19

    申请号：US161655

    申请日：1993-12-02

    申请人： Eiji Nagatake ,  Kazuo Kubo

    发明人： Eiji Nagatake ,  Kazuo Kubo

    IPC分类号： H04J3/00 ,  H04J3/04 ,  H04J3/06 ,  H04L7/08 ,  H04J3/12

    CPC分类号： H04J3/0623

    摘要： A first frame counter generates a position signal for an input subframe address which is synchronized with an input clock signal based on an input frame phase signal. The first frame counter also generates a write address enabling signal. A subframe type detector generates a write/read control signal based on an input frame signal. Depending upon the position signal for the input subframe address, the write address enabling signal and the write/read control signal, a first subframe phase synchronization device and a second to nth subframe phase synchronization device control a buffer corresponding to 1/m of a frame data amount by a write address, where m (n>=m) is a multiplexing number. The first subframe phase synchronization device and the second to mth subframe phase synchronization device writes data corresponding to a first to mth input subframe signal based on the input frame signal into a buffer respectively. An input relative phase is synchronized with a standard relative phase. The synchronized signal is output as a synchronized frame signal.

    摘要翻译： 第一帧计数器基于输入帧相位信号产生与输入时钟信号同步的输入子帧地址的位置信号。 第一帧计数器还产生写入地址使能信号。 子帧类型检测器基于输入帧信号生成写/读控制信号。 根据输入子帧地址的位置信号，写入地址使能信号和写入/读取控制信号，第一子帧相位同步装置和第二至第n个子帧同步装置控制对应于帧的1 / m的缓冲器 数据量写入地址，其中m（n> = m）是复用数。 第一子帧相位同步装置和第二至第m子帧同步装置分别将基于输入帧信号的与第一至第m输入子帧信号相对应的数据写入缓冲器。 输入相对相位与标准相对相位同步。 同步信号作为同步帧信号输出。