公开(公告)号：US20050062500A1

公开(公告)日：2005-03-24

申请号：US10671416

申请日：2003-09-24

Applicant: Varghese George

Inventor： Varghese George

IPC: H03K19/0175 ,  H03K19/094

CPC classification number: H03K19/01759

Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

Abstract translation: 本发明涉及用于编程这种缓冲器的可编程双向缓冲器和方法。 根据本发明的一个方面的一种方法是配置包括第一和第二信号节点的双向缓冲器的方法。 该方法包括在第一和第二信号节点之一上应用配置信号并且响应于所应用的配置信号来配置缓冲器。

公开(公告)号：US06823418B2

公开(公告)日：2004-11-23

申请号：US09896395

申请日：2001-06-29

Applicant: Brian K. Langendorf ,  Varghese George

Inventor： Brian K. Langendorf ,  Varghese George

IPC: G06F1300

CPC classification number: G06F13/105

Abstract: Virtual PCI bus appears from the perspective of a computer program to be a part of a physical hierarchical PCI bus structure residing behind a host-to-PCI bridge. Devices that are physically located on the host bus side of the host-to-PCI bridge may appear as virtual devices residing on the virtual PCI bus allowing the physical devices to participate in device independent initialization and system resource allocation generally available only to PCI compliant devices. Processor initiated host bus cycles targeted to the virtual PCI device may be intercepted and redirected to the physical device.

Abstract translation: 虚拟PCI总线从计算机程序的角度出现，成为位于主机到PCI桥后面的物理分层PCI总线结构的一部分。 物理上位于主机到PCI桥接器主机总线侧的设备可以显示为位于虚拟PCI总线上的虚拟设备，允许物理设备参与独立于设备的初始化和通常仅适用于PCI兼容设备的系统资源分配 。 针对虚拟PCI设备的处理器发起的主机总线周期可能会被拦截并重定向到物理设备。

公开(公告)号：US06779122B2

公开(公告)日：2004-08-17

申请号：US09748612

申请日：2000-12-26

Applicant: Varghese George ,  Tim W. Chan

Inventor： Varghese George ,  Tim W. Chan

IPC: G06F130

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3237 ,  G06F9/30083 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/4418 ,  Y02D10/128

Abstract: A micro-code sequence to reduce the rate of change of current required by a processor coming out of a sleep mode when the processor clock is resumed. After stopping the instruction fetch unit, an instruction with a long latency, or execution time, can be initiated by the micro-code before the processor clock is stopped to enter a sleep mode. When the sleep mode is exited by resuming the processor clock, the instruction with the long execution time is completed before restarting the instruction fetch unit. This prevents a portion of the processor circuitry from resuming operation immediately when the clock is resumed, which also delays some of the current demands made by that portion of the circuitry. This creates a more gradual increase in the current required by the processor when exiting a sleep mode.

Abstract translation: 一种微码序列，用于当处理器时钟恢复时，降低处理器从休眠模式出来所需的电流变化率。 在停止指令提取单元之后，在处理器时钟停止进入睡眠模式之前，可以通过微代码启动具有长延迟或执行时间的指令。 当通过恢复处理器时钟退出睡眠模式时，在重新启动指令获取单元之前完成执行时间长的指令。 这样可以防止处理器电路的一部分在恢复时钟时立即恢复操作，这也延迟了该电路部分所产生的一些当前需求。 这会在退出睡眠模式时使处理器所需的电流逐渐增加。

公开(公告)号：US06772241B1

公开(公告)日：2004-08-03

申请号：US09676463

申请日：2000-09-29

Applicant: Varghese George ,  Edward Gamsaragan ,  Vladimir M. Pentkovski ,  Deep K. Buch ,  Paul Zagacki

Inventor： Varghese George ,  Edward Gamsaragan ,  Vladimir M. Pentkovski ,  Deep K. Buch ,  Paul Zagacki

IPC: G06F500

CPC classification number: G06F9/4812 ,  G06F13/24 ,  Y02D10/14 ,  Y02D10/24

Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using either a bus-based message or a dedicated interrupt line.

Abstract translation: 描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。 中断由计算机系统中的各种平台设备生成。 根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。 可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。

公开(公告)号：US06745298B2

公开(公告)日：2004-06-01

申请号：US09334060

申请日：1999-06-16

Applicant: Steven J. Spangler ,  Varghese George

Inventor： Steven J. Spangler ,  Varghese George

IPC: G06F1200

CPC classification number: G06F12/0831

Abstract: A method and apparatus for processing data is described. A request such as a multiprocessor snoop request for data is received from a bus. A determination is made as to whether a cache contains the data. The data is placed in a buffer. A determination is made as to whether the bus can receive the data. The data is sent to the bus.

Abstract translation: 描述用于处理数据的方法和装置。 从总线接收诸如数据的多处理器窥探请求之类的请求。 确定高速缓存是否包含数据。 数据放在缓冲区中。 确定总线是否可以接收数据。 数据发送到总线。

公开(公告)号：US06704877B2

公开(公告)日：2004-03-09

申请号：US09751530

申请日：2000-12-29

Applicant: Leslie E. Cline ,  Varghese George ,  David Wyatt

Inventor： Leslie E. Cline ,  Varghese George ,  David Wyatt

IPC: G06F100

CPC classification number: G06F9/30101 ,  G06F1/3203

Abstract: A device controller can have multiple device performance states (DPS), which represent different levels of performance vs. power consumption during operation. The device controller can include a DPS status register that can be read by a processor, to indicate the current DPS, and a DPS control register that can be written by the processor, to change the current DPS to a desired DPS. The controller may also have a processor performance state (PPS) status register which can be used to affect the desired choice of DPS based on the performance state of the processor. Each of the registers can be accessed by the device driver for that device controller. The DPS of multiple devices can be coordinated to achieve an improved system-level reduction in power consumption, while maintaining sufficient operational capability.

Abstract translation: 设备控制器可以具有多个设备性能状态（DPS），其表示不同的性能水平与操作期间的功率消耗。 设备控制器可以包括可由处理器读取，指示当前DPS的DPS状态寄存器和可由处理器写入的DPS控制寄存器，以将当前DPS改变为期望的DPS。 控制器还可以具有处理器性能状态（PPS）状态寄存器，其可以用于基于处理器的性能状态影响DPS的期望选择。 每个寄存器都可以由该设备控制器的设备驱动程序访问。 可以协调多个设备的DPS，以在维持足够的操作能力的同时实现功率消耗的系统级降低。

公开(公告)号：US06636939B1

公开(公告)日：2003-10-21

申请号：US09607537

申请日：2000-06-29

Applicant: Varghese George

Inventor： Varghese George

IPC: G06F1200

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/0831

Abstract: A memory interface unit is described having a first interface to receive a first request from a processor where the first request has an attribute. The memory interface unit also has a second interface to receive a second request from the processor where the second request does not have the attribute. The memory interface unit also has a third interface to read/write information from/to a system memory. A method is also described that involves forwarding a processor request along a first path to a memory interface unit if the request has one or more attributes; and forwarding the request along a second path to the memory interface unit if the processor request does not have the one or more attributes.

Abstract translation: 描述了存储器接口单元，其具有第一接口以从处理器接收第一请求，其中第一请求具有属性。 存储器接口单元还具有第二接口，用于从处理器接收第二请求，其中第二请求不具有该属性。 存储器接口单元还具有用于从/向系统存储器读取/写入信息的第三接口。 还描述了一种方法，其涉及如果所述请求具有一个或多个属性，则将处理器请求沿着第一路径转发到存储器接口单元; 以及如果所述处理器请求不具有所述一个或多个属性，则将所述请求沿着第二路径转发到所述存储器接口单元。