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公开(公告)号：US07069367B2
公开(公告)日：2006-06-27
申请号：US09752042
申请日：2000-12-29
申请人： David I. Poisner , Leslie E. Cline
发明人： David I. Poisner , Leslie E. Cline
IPC分类号： G06F13/24
CPC分类号： G06F1/3228 , G06F13/24
摘要： An embodiment of a system for avoiding race conditions when using edge-triggered interrupts includes a processor that asserts an interrupt pending signal in response to the receipt of an edge-triggered interrupt. A power management device receives the interrupt pending signal. If the processor is in a low power state when it asserts the interrupt pending signal, then the power management device causes the processor to enter a high power state to allow the processor to service the pending interrupt.
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2.发明授权Peripheral interface circuit which snoops commands to determine when to perform DMA protocol translation 失效外围接口电路侦听命令来确定何时执行DMA协议转换
公开(公告)号：US5655145A
公开(公告)日：1997-08-05
申请号：US329554
申请日：1994-10-25
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.
摘要翻译： 用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口，使用流水线架构来增加可用数据传输带宽的使用。 为了实现上述目的，耦合在计算机本地总线和外围接口之间的LBPI被提供为流水线架构，其包括预读缓冲器，预读计数器，数据输出锁存器和控制状态 机器配置寄存器。 在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。 通过保持已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令以智能地预测随后的读取数据传输命令的发生，来进一步提高读取前进操作的效率。 控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。 在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。 在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。 在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。 在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。 在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。
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公开(公告)号：US09170626B2
公开(公告)日：2015-10-27
申请号：US13023355
申请日：2011-02-08
CPC分类号： G06F1/3203 , G06F1/206 , Y02D10/16 , Y10T307/438
摘要： For one disclosed embodiment, a lower limit for a power consumption device may be identified. Performance of the power consumption device may be reduced in response to a determination that a temperature corresponding to the power consumption device exceeds a threshold. Performance reduction may be limited based on the lower limit. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，可以识别功耗装置的下限。 响应于与功率消耗装置相对应的温度超过阈值的确定，可以降低功耗装置的性能。 性能下降可能受限于下限。 还公开了其他实施例。
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公开(公告)号：US07472289B2
公开(公告)日：2008-12-30
申请号：US11019791
申请日：2004-12-21
CPC分类号： G06F1/3203
摘要： An audio noise mitigation approach. For one aspect, a first voltage associated with a first power management state is provided. A signal responsive to an indication associated with at least a first type of periodic exit event is received and responsive to the signal, a transition to a second voltage associated with a second state is initiated, a rate of the transition to the second voltage being slower than a similar voltage transition initiated in response to a non-periodic exit event.
摘要翻译： 音频噪声缓解方法。 一方面，提供与第一电源管理状态相关联的第一电压。 接收响应于与至少第一类型的周期性退出事件相关联的指示的信号并且响应于该信号，开始向与第二状态相关联的第二电压的转变，到第二电压的转变的速率较慢 而不是响应于非周期性退出事件而发起的类似电压转换。
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5.发明授权公开(公告)号：US07373534B2
公开(公告)日：2008-05-13
申请号：US11165157
申请日：2005-06-23
申请人： Leslie E. Cline
发明人： Leslie E. Cline
IPC分类号： G06F1/00
CPC分类号： G06F1/3215
摘要： Systems and methods of managing power consumption provide for placing a processor in a non-snoopable state while a storage interface associated with the processor is enabled for bus mastering. In one embodiment, the bus mastering results in traffic between the storage interface and a storage device, where the traffic is monitored and the processor is placed a snoopable state when traffic is moving, and in the non-snoopable idle state if the traffic ceases for a period of time.
摘要翻译： 管理功耗的系统和方法提供了将处理器置于不可窥探状态，而与处理器相关联的存储接口能够用于总线主控。 在一个实施例中，总线主控导致存储接口和存储设备之间的业务，其中监视业务，并且当业务正在移动时将处理器置于可窥探状态，并且处于不可窥探空闲状态，如果业务停止 一段时间。
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公开(公告)号：US07281074B2
公开(公告)日：2007-10-09
申请号：US11171833
申请日：2005-06-29
摘要： In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor and the memory. The USB controller includes a local memory to cache at least one activity descriptor of at least a portion of a periodic schedule having multiple frames stored in the main memory. The USB controller defers to service an active USB device described by one of the activity descriptors until a corresponding frame is scheduled to be serviced subsequently. Other methods and apparatuses are also described.
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公开(公告)号：US07231468B2
公开(公告)日：2007-06-12
申请号：US10456185
申请日：2003-06-06
申请人： Leslie E. Cline
发明人： Leslie E. Cline
CPC分类号： G06F13/124 , Y02D10/14
摘要： One embodiment includes a future activity list (FAL) maintained within a peripheral bus host controller. The FAL includes information indicating for a number of peripheral bus frames whether those frames will have activity or are null. For frames that will have activity, the host controller performs a system memory read to gather information required to process the active frame. For frames that are null, the host controller does not perform the system memory read. A bus master status bit is pegged (continually set to “true”) by the host controller only when the host controller is processing an active frame. Because the bus master status bit is not pegged by the host controller during null frames, there is greater opportunity for an operating system to enter lower power states.
摘要翻译： 一个实施例包括维护在外围总线主机控制器内的未来活动列表（FAL）。 FAL包括指示多个外围总线帧的信息，无论这些帧是否具有活动或为空。 对于具有活动的帧，主机控制器执行系统内存读取，以收集处理活动帧所需的信息。 对于为空的帧，主机控制器不执行系统内存读取。 只有当主机控制器处理活动帧时，总线主控状态位被主机控制器固定（连续设置为“真”）。 由于总线主控状态位在空帧期间不被主机控制器挂起，所以操作系统进入较低功率状态的机会更大。
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公开(公告)号：US07225347B2
公开(公告)日：2007-05-29
申请号：US11300716
申请日：2005-12-13
申请人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
发明人： Xia Dai , John W. Horigan , Millind Mittal , Leslie E. Cline
CPC分类号： G06F1/3203 , G06F12/0891
摘要： In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicated the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.
摘要翻译： 根据本发明的实施例，启动触发事件以将处理器置于低功率状态。 根据电源状态信号，处理器可能进入或不进入低功率状态时刷新高速缓存。 功率状态信号可以指示与将低处理器置于低功率状态相关联的功率降低的相对优先级，而无需首先刷新高速缓存，而与高功率状态中的电压降低相关联的高速缓存中的软错误率的增加。
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9.发明授权Computer peripheral device that remains operable when central processor operations are suspended 有权当中央处理器操作暂停时，可以保持可操作的计算机外围设备公开(公告)号：US06748548B2
公开(公告)日：2004-06-08
申请号：US09752627
申请日：2000-12-29
IPC分类号： G06F126
CPC分类号： G06F1/3215 , G06F13/4022
摘要： A peripheral device having a circuit to detect the power management state of a central processor, a first interface to receive data, and a second interface to couple the peripheral device to the central processor. The peripheral device prevents data transfers that would cause the central processor to change from a second power management state to a first power management state if the central processor is in the second power management state.
摘要翻译： 具有检测中央处理器的电源管理状态的电路的外围设备，用于接收数据的第一接口以及将外围设备耦合到中央处理器的第二接口。 如果中央处理器处于第二电源管理状态，则外围设备防止将导致中央处理器从第二电源管理状态改变到第一电源管理状态的数据传输。
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公开(公告)号：US06871252B1
公开(公告)日：2005-03-22
申请号：US09540676
申请日：2000-03-31
申请人： Leslie E. Cline
发明人： Leslie E. Cline
CPC分类号： G06F13/4081
摘要： A method and apparatus for performing logical attachments and detachments in a hot-plug-in data bus is described. A hot-plug-in data bus may utilize pull-down resistors to keep bus signals near a low voltage level when bus units are physically detached. Active pull-up resistors may then raise the bus signals away from ground when the bus units are physically attached via cabling or other forms of interconnection. The pull-up resistors may be switched away from the pull-up voltage source, which allows the remaining pull-down resistors to pull the bus signals down to the voltage levels corresponding to physical detachment of the cabling.
摘要翻译： 描述用于在热插拔数据总线中执行逻辑附件和拆卸的方法和装置。 当总线单元物理分离时，热插拔数据总线可以利用下拉电阻器将总线信号保持在低电压电平附近。 然后，当总线单元通过布线或其他形式的互连物理连接时，主动上拉电阻可以将总线信号提升离地。 上拉电阻可以从上拉电压源切换，这允许剩余的下拉电阻将总线信号拉至与布线的物理分离相对应的电压电平。
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