公开(公告)号：US20150186313A1

公开(公告)日：2015-07-02

申请号：US14141828

申请日：2013-12-27

Applicant: Inder M. Sodhi ,  Joydeep Ray ,  Varghese George

Inventor： Inder M. Sodhi ,  Joydeep Ray ,  Varghese George

IPC: G06F13/36 ,  G06F9/50

CPC classification number: G06F13/36 ,  G06F9/52

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

Abstract translation: 根据本文公开的实施例，提供了用于管理多个处理设备之间的共享资源的系统和方法。 处理器可以包括包括包括非相干数据的第一非相干硬件块（hb）的第一处理设备和包括包括非相干数据的第二非相干hb的第二处理设备。 处理器还可以包括与第一非相干hb和第二非相干hb通信的第一hb以跟踪和共享第一和第二处理设备之间的非相干数据。

公开(公告)号：US08516285B2

公开(公告)日：2013-08-20

申请号：US13074871

申请日：2011-03-29

Applicant: Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey ,  Eric Heit

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey ,  Eric Heit

IPC: G06F1/26 ,  G06F1/00 ,  G05D3/12 ,  H01Q11/12 ,  H04M1/00

CPC classification number: G06F1/3203

Abstract: Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.

公开(公告)号：US20130013945A1

公开(公告)日：2013-01-10

申请号：US13619998

申请日：2012-09-14

Applicant: Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract translation: 本发明的实施例涉及一种用于零电压处理器睡眠状态的方法和装置。 处理器可以包括专用高速缓存存储器。 电压调节器可以耦合到处理器以向处理器提供工作电压。 在处理器转换到零电压电源管理状态期间，电压调节器施加到处理器的工作电压可以减小到大约零，并且与处理器相关联的状态变量可以被保存到专用高速缓冲存储器。

公开(公告)号：US20090024799A1

公开(公告)日：2009-01-22

申请号：US11880357

申请日：2007-07-20

Applicant: Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  Jose Allarey

IPC: G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.

Abstract translation: 根据至少一个实施例的在低功率模式下保持缓存信息的技术。 在一个实施例中，存储在处理器的本地高速缓存中的信息在处理器被置于低功率模式之前被保存到共享高速缓存，使得其他处理器可以从共享高速缓存访​​问信息，而不是使低功率模式处理器从 低功耗模式来访问其本地缓存。

公开(公告)号：US20080005592A1

公开(公告)日：2008-01-03

申请号：US11477751

申请日：2006-06-28

Applicant: Jose Allarey ,  Varghese George ,  Sanjeev Jahagirdar ,  Oren Lamdan

Inventor： Jose Allarey ,  Varghese George ,  Sanjeev Jahagirdar ,  Oren Lamdan

IPC: G06F1/00

CPC classification number: G06F1/206

Abstract: A method, system, and apparatus to enable at least one active core in a multi-core processor to operate at a higher operating point while at least one other core in the multi-core processor is in an idle state. When the idle core exits the idle state, the operating point may be reduced after a hysteresis timer has expired.

Abstract translation: 一种使多核处理器中的至少一个活动核心能够在较高工作点运行并且多核处理器中的至少一个其他核心处于空闲状态的方法，系统和装置。 当空闲磁芯退出空闲状态时，在滞后计时器到期后，工作点可能会减少。

公开(公告)号：US07149645B2

公开(公告)日：2006-12-12

申请号：US11024679

申请日：2004-12-30

Applicant: Kedar Mangrulkar ,  Sanjeev Jahagirdar ,  Varghese George ,  Venkatesh Prasanna ,  Inder Sodhi

Inventor： Kedar Mangrulkar ,  Sanjeev Jahagirdar ,  Varghese George ,  Venkatesh Prasanna ,  Inder Sodhi

IPC: G01K1/00 ,  G06F15/00

CPC classification number: G01K7/42 ,  G01K3/005

Abstract: A device and method for continually monitoring multiple thermal sensors located at hotspots across a processor. The sensors are connected to a sensor cycling and selection block located at a periphery of the die. The output from the sensor selection block is converted into a digital temperature code. Based on the digital temperature code, thermal events trigger various thermal controls. The thermal event triggers may be software-programmable, providing flexible temperature management.

Abstract translation: 一种用于连续监测位于热点处的多个热传感器的装置和方法。 传感器连接到位于模具周边的传感器循环和选择块。 传感器选择块的输出转换为数字温度代码。 基于数字温度代码，热事件触发各种热控制。 热事件触发器可以是软件可编程的，提供灵活的温度管理。

公开(公告)号：US20060164123A1

公开(公告)日：2006-07-27

申请号：US11393934

申请日：2006-03-30

Applicant: Varghese George

Inventor： Varghese George

IPC: H03K19/0175

CPC classification number: H03K19/01759

Abstract: The present invention is directed to programmable bidirectional buffers and methods for programming such buffers. One method of according to an aspect of the present invention is a method of configuring a bidirectional buffer including first and second signal nodes. The method includes applying a configuration signal on one of the first and second signal nodes and configuring the buffer responsive to the applied configuration signal.

Abstract translation: 本发明涉及用于编程这种缓冲器的可编程双向缓冲器和方法。 根据本发明的一个方面的一种方法是配置包括第一和第二信号节点的双向缓冲器的方法。 该方法包括在第一和第二信号节点之一上应用配置信号并且响应于所应用的配置信号来配置缓冲器。

公开(公告)号：US06976099B2

公开(公告)日：2005-12-13

申请号：US10865220

申请日：2004-06-09

Applicant: Varghese George ,  Edward Gamsaragan ,  Vladimir M. Pentkovski ,  Deep K. Buch ,  Paul Zagacki

Inventor： Varghese George ,  Edward Gamsaragan ,  Vladimir M. Pentkovski ,  Deep K. Buch ,  Paul Zagacki

IPC: G06F9/48 ,  G06F13/24 ,  G06F5/00

CPC classification number: G06F9/4812 ,  G06F13/24 ,  Y02D10/14 ,  Y02D10/24

Abstract: A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.

Abstract translation: 描述了一种用于向具有独立操作系统的多个处理器之一选择性地传递中断的方法和装置。 中断由计算机系统中的各种平台设备生成。 根据系统的操作模式，控制器被配置为在主处理器关闭时向协处理器传送中断，而不打开主机处理器。 可以使用基于总线的消息或专用中断线将中断传送到正确的处理器。

公开(公告)号：US20050091548A1

公开(公告)日：2005-04-28

申请号：US10696469

申请日：2003-10-28

Applicant: Varghese George ,  Stephen Gunther ,  Sanjeev Jahagirdar ,  Inder Sodhi

Inventor： Varghese George ,  Stephen Gunther ,  Sanjeev Jahagirdar ,  Inder Sodhi

IPC: G06F1/20 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: Methods and circuits to define a thermal operating mode for a integrated device by defining an operating voltage and a frequency range.

Abstract translation: 通过定义工作电压和频率范围来定义集成器件的热操作模式的方法和电路。

公开(公告)号：US09727388B2

公开(公告)日：2017-08-08

申请号：US13995340

申请日：2011-12-29

Applicant: Sanjeev S. Jahagirdar ,  Varghese George ,  Inder Sodhi

Inventor： Sanjeev S. Jahagirdar ,  Varghese George ,  Inder Sodhi

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/5083 ,  G06F9/30003 ,  G06F9/4856

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.