公开(公告)号：US06247094B1

公开(公告)日：2001-06-12

申请号：US08996110

申请日：1997-12-22

Applicant: Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang ,  Tim W. Chan

Inventor： Harsh Kumar ,  Gunjeet D. Baweja ,  Cheng-Feng Chang ,  Tim W. Chan

IPC: G06F1200

CPC classification number: G06F12/0895 ,  G06F12/0862 ,  G06F12/0864 ,  G06F2212/6082

Abstract: The present invention provides an improved cache memory architecture with way prediction. The improved architecture entails placing the address tag array of a cache memory on the central processing unit core (i.e. the microprocessor chip), while the cache data array remains off the microprocessor chip. In addition, a way predictor is provided in conjunction with the improved memory cache architecture to increase the overall performance of the cache memory system.

Abstract translation: 本发明提供了一种具有方式预测的改进的高速缓存存储器架构。 改进的架构需要将高速缓冲存储器的地址标签阵列放置在中央处理单元核心（即微处理器芯片）上，而高速缓存数据阵列保留在微处理器芯片之外。 此外，结合改进的存储器高速缓存结构提供方式预测器以增加高速缓冲存储器系统的整体性能。

公开(公告)号：US06779122B2

公开(公告)日：2004-08-17

申请号：US09748612

申请日：2000-12-26

Applicant: Varghese George ,  Tim W. Chan

Inventor： Varghese George ,  Tim W. Chan

IPC: G06F130

CPC classification number: G06F1/3206 ,  G06F1/26 ,  G06F1/3237 ,  G06F9/30083 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/4418 ,  Y02D10/128

Abstract: A micro-code sequence to reduce the rate of change of current required by a processor coming out of a sleep mode when the processor clock is resumed. After stopping the instruction fetch unit, an instruction with a long latency, or execution time, can be initiated by the micro-code before the processor clock is stopped to enter a sleep mode. When the sleep mode is exited by resuming the processor clock, the instruction with the long execution time is completed before restarting the instruction fetch unit. This prevents a portion of the processor circuitry from resuming operation immediately when the clock is resumed, which also delays some of the current demands made by that portion of the circuitry. This creates a more gradual increase in the current required by the processor when exiting a sleep mode.

Abstract translation: 一种微码序列，用于当处理器时钟恢复时，降低处理器从休眠模式出来所需的电流变化率。 在停止指令提取单元之后，在处理器时钟停止进入睡眠模式之前，可以通过微代码启动具有长延迟或执行时间的指令。 当通过恢复处理器时钟退出睡眠模式时，在重新启动指令获取单元之前完成执行时间长的指令。 这样可以防止处理器电路的一部分在恢复时钟时立即恢复操作，这也延迟了该电路部分所产生的一些当前需求。 这会在退出睡眠模式时使处理器所需的电流逐渐增加。

公开(公告)号：US5274277A

公开(公告)日：1993-12-28

申请号：US938934

申请日：1992-09-01

Applicant: Tim W. Chan

Inventor： Tim W. Chan

IPC: G06F7/02 ,  H03K19/0944 ,  H03K19/003

CPC classification number: G06F7/02 ,  H03K19/09448

Abstract: A circuit for providing an OR function on the outputs of at least two MOS logic circuits. The circuit has an output node capable of being in a first or second logic state and being responsive to a first or second path. The first path includes multiple WIRED-OR logic circuits which function as an OR gate on the outputs of MOS logic circuits. The results of the operation cause the architecture output to transition into the first state. The second path is skewed for the second state, such that the transition into the second state occurs fast. Thus, the transition of the output node from the second state to the first state and vice versa is provided by one path, such that the overall ORing function occurs faster.

Abstract translation: 一种用于在至少两个MOS逻辑电路的输出上提供OR功能的电路。 电路具有能够处于第一或第二逻辑状态并且响应于第一或第二路径的输出节点。 第一路径包括多个WIRED-OR逻辑电路，其作为MOS逻辑电路的输出上的或门。 操作的结果使架构输出转变到第一个状态。 对于第二状态，第二路径偏斜，使得进入第二状态的转变发生得很快。 因此，输出节点从第二状态转换到第一状态，反之亦然，由一个路径提供，使得整体ORing功能发生得更快。