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    Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit
    73.
    发明授权
    Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit 失效
    通过ALU访问使用范围索引访问不同范围的变量的执行指令在过程调用和退出时自动更改

    公开(公告)号：US07475229B2

    公开(公告)日：2009-01-06

    申请号：US11354670

    申请日：2006-02-14

    申请人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel F. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    发明人： Wajdi K. Feghali ,  William C. Hasenplaugh ,  Gilbert M. Wolrich ,  Daniel F. Cutter ,  Vinodh Gopal ,  Gunnar Gaubatz

    IPC分类号： G06F9/302

    CPC分类号： G06F21/602

    摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.

    摘要翻译： 通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。 控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联 逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合 响应一个指令。

    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES)
    76.
    发明申请
    ARCHITECTURE AND INSTRUCTION SET FOR IMPLEMENTING ADVANCED ENCRYPTION STANDARD (AES) 有权
    实施高级加密标准（AES）的架构和指导

    公开(公告)号：US20120002804A1

    公开(公告)日：2012-01-05

    申请号：US13088088

    申请日：2011-04-15

    申请人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    发明人： Shay Gueron ,  Wajdi K. Feghali ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F21/602 ,  H04L9/14 ,  H04L2209/24

    摘要： A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.

    摘要翻译： 提供了一种用于通用处理器的灵活的aes指令，其使用n次循环执行aes加密或解密，其中n包括标准的一组轮{10,12,14}。 提供了一个参数，以允许选择一轮的类型，即是否是“最后一轮”。 除了标准aes之外，灵活的aes指令允许指定具有20发的AES类密码或“一轮”通过。

    Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor
    77.
    发明授权
    Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor 有权
    128位处理器上的SKEIN256 SHA3算法指令集

    公开(公告)号：US08953785B2

    公开(公告)日：2015-02-10

    申请号：US13631143

    申请日：2012-09-28

    申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal

    发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0643 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036

    摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.

    摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联 具有存储多个偶数字的第二存储位置和第三操作数。 处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮 由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。

    INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM
    78.
    发明申请
    INSTRUCTION SET FOR MESSAGE SCHEDULING OF SHA256 ALGORITHM 有权
    SHA256算法的消息调度指令集

    公开(公告)号：US20140093069A1

    公开(公告)日：2014-04-03

    申请号：US13631165

    申请日：2012-09-28

    申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Sean M. Gulley

    发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Vinodh Gopal ,  Sean M. Gulley

    IPC分类号： H04L9/28

    CPC分类号： G09C1/00 ,  G06F9/30007 ,  H04L9/0643 ,  H04L2209/125

    摘要： A processor includes a first execution unit to receive and execute a first instruction to process a first part of secure hash algorithm 256 (SHA256) message scheduling operations, the first instruction having a first operand associated with a first storage location to store a first set of message inputs and a second operand associated with a second storage location to store a second set of message inputs. The processor further includes a second execution unit to receive and execute a second instruction to process a second part of the SHA256 message scheduling operations, the second instruction having a third operand associated with a third storage location to store an intermediate result of the first part and a third set of message inputs and a fourth operand associated with a fourth storage location to store a fourth set of message inputs.

    摘要翻译： 处理器包括第一执行单元，用于接收和执行第一指令以处理安全散列算法256（SHA256）消息调度操作的第一部分，所述第一指令具有与第一存储位置相关联的第一操作数，以存储第一组 消息输入和与第二存储位置相关联的第二操作数，以存储第二组消息输入。 所述处理器还包括第二执行单元，用于接收和执行用于处理所述SHA256消息调度操作的第二部分的第二指令，所述第二指令具有与第三存储位置相关联的第三操作数，以存储所述第一部分的中间结果;以及 第三组消息输入和与第四存储位置相关联的第四操作数，以存储第四组消息输入。

    INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR
    79.
    发明申请
    INSTRUCTION SET FOR SKEIN256 SHA3 ALGORITHM ON A 128-BIT PROCESSOR 有权
    128位处理器的SKEIN256 SHA3算法指令集

    公开(公告)号：US20140093068A1

    公开(公告)日：2014-04-03

    申请号：US13631143

    申请日：2012-09-28

    申请人： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal

    发明人： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0643 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036

    摘要： According to one embodiment, a processor includes an instruction decoder to receive a first instruction to perform first SKEIN256 MIX-PERMUTE operations, the first instruction having a first operand associated with a first storage location to store a plurality of odd words, a second operand associated with a second storage location to store a plurality of even words, and a third operand. The processor further includes a first execution unit coupled to the instruction decoder, in response to the first instruction, to perform multiple rounds of the first SKEIN256 MIX-PERMUTE operations based on the odd words and even words using a first rotate value obtained from a third storage location indicated by the third operand, and to store new odd words in the first storage location indicated by the first operand.

    摘要翻译： 根据一个实施例，处理器包括指令解码器，用于接收执行第一SKEIN256 MIX-PERMUTE操作的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储多个奇数字，第二操作数相关联 具有存储多个偶数字的第二存储位置和第三操作数。 处理器还包括响应于第一指令而耦合到指令解码器的第一执行单元，使用从第三指令获得的第一旋转值，基于奇数字和偶数字进行第一SKEIN256 MIX-PERMUTE操作的多轮 由第三操作数指示的存储位置，并将新的奇数字存储在由第一操作数指示的第一存储位置中。