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    Methods and apparatus for using tones in a wireless communication system
    71.
    发明申请
    Methods and apparatus for using tones in a wireless communication system 有权
    在无线通信系统中使用音调的方法和装置

    公开(公告)号：US20070242763A1

    公开(公告)日：2007-10-18

    申请号：US11486602

    申请日：2006-07-14

    申请人： Junyi Li ,  Tom Richardson

    发明人： Junyi Li ,  Tom Richardson

    IPC分类号： H04K1/10

    CPC分类号： H04L5/023 ,  H04L27/261

    摘要： Methods and apparatus for allocating tones for communications in the strip-symbol periods in an OFDM system are described. In a strip-symbol, the signal is transmitted using the tones in a tone subset, which is selected from a predetermined set of tone subsets according to a fixed schedule sequence. Adjacent base stations and sectors use the same set of tone subsets but different schedule sequence to minimize the number of collisions between the tone subsets used in adjacent sectors and neighboring cells.

    摘要翻译： 描述在OFDM系统中的带符号周期中分配用于通信的音调的方法和装置。 在条形符号中，使用音调子集中的音调发送信号，该音调子集根据固定的调度序列从预定的音调子集组中选择。 相邻的基站和扇区使用相同的一组音调子集，但是使用不同的调度序列来最小化在相邻扇区和相邻小区中使用的音调子集之间的冲突次数。

    LCPC decoding methods and apparatus
    72.
    发明授权
    LCPC decoding methods and apparatus 有权
    LCPC解码方法和装置

    公开(公告)号：US08595569B2

    公开(公告)日：2013-11-26

    申请号：US12128516

    申请日：2008-05-28

    申请人： Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

    发明人： Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

    IPC分类号： G06F11/00

    CPC分类号： H04L1/0057 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6513 ,  H03M13/6516 ,  H04L1/0045

    摘要： A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

    摘要翻译： 描述了一种灵活且相对硬件有效的LDPC解码器。 该解码器可以用低于用于控制解码过程的代码结构的完全并行性的并行级别来实现。 用于描述代码结构的相对简单的控制代码的每个命令可以被多次存储和执行以完成码字的解码。 使用相同的一组控制码指令支持不同的码字长度，但是根据码字长度，代码被实现不同的次数。 解码器可以通过简单地改变表示码字长度的代码提升因子而不需要改变存储的代码描述信息来切换不同长度的解码码字，并用于控制解码过程。 当解码短于最大支持码字长度的码字时，一些块存储位置可能不被使用。

    LDPC encoding methods and apparatus
    73.
    发明授权
    LDPC encoding methods and apparatus 失效
    LDPC编码方法和装置

    公开(公告)号：US08533568B2

    公开(公告)日：2013-09-10

    申请号：US12050119

    申请日：2008-03-17

    申请人： Tom Richardson ,  Hui Jin

    发明人： Tom Richardson ,  Hui Jin

    IPC分类号： G11C29/00

    CPC分类号： H03M13/6508 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

    摘要： A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

    摘要翻译： 描述了一种灵活且相对硬件高效的LDPC编码器。 编码器可以以小于平行度的水平来实现，该并行度小于用于控制编码过程的代码结构的完全并行性。 用于描述代码结构的相对简单的微代码的每个命令可以被多次存储和执行以完成代码字的编码。 可以使用相同的微代码指令集来支持不同的码字长度，但是根据所选择的使用的提升因子，代码被实现不同的次数。 LDPC编码器可以通过简单地改变用于控制编码处理的代码提升因子来切换不同长度的编码码字，而不需要改变存储的代码描述信息。 当编码比最大支持的码字长度短的码字时，一些块存储位置和/或寄存器可能不被使用。

    System and method for tracking vehicles and containers
    74.
    发明授权
    System and method for tracking vehicles and containers 有权
    跟踪车辆和集装箱的系统和方法

    公开(公告)号：US07755541B2

    公开(公告)日：2010-07-13

    申请号：US12028894

    申请日：2008-02-11

    申请人： David S. Wisherd ,  Robert W. Boyd ,  Tom Richardson ,  Santiago Romero ,  Michael A. Wohl

    发明人： David S. Wisherd ,  Robert W. Boyd ,  Tom Richardson ,  Santiago Romero ,  Michael A. Wohl

    IPC分类号： G01S5/14 ,  H04L12/58

    CPC分类号： G01S19/07 ,  G01S19/09

    摘要： A location system for tracking assets within a terminal includes a Differential Global Positioning System (DGPS) reference receiver within the terminal that receives GPS signals and generates DGPS correction data. In one aspect, a roving receiver unit is carried by an asset to be tracked within the terminal. It includes a GPS receiver that receives GPS signals and the DGPS correction data from the DGPS reference receiver. A tag transmitter transmits a wireless RF signal containing GPS location data based on received GPS signals and DGPS correction data. At least one access point is positioned within the terminal for receiving the wireless RF signal from the tag transmitter. A processor is operatively connected to the at least one access point for receiving GPS location data and determining a location of the asset to be tracked.

    摘要翻译： 用于跟踪终端内的资产的定位系统包括终端内的差分全球定位系统（DGPS）参考接收机，其接收GPS信号并产生DGPS校正数据。 在一个方面，粗纱接收机单元由在终端内跟踪的资产携带。 它包括GPS接收器，其接收来自DGPS参考接收机的GPS信号和DGPS校正数据。 标签发送器基于接收到的GPS信号和DGPS校正数据发送包含GPS位置数据的无线RF信号。 至少一个接入点位于终端内，用于从标签发射器接收无线RF信号。 处理器可操作地连接到所述至少一个接入点，用于接收GPS位置数据并确定要跟踪的资产的位置。

    SYSTEM AND METHOD FOR TRACKING VEHICLES AND CONTAINERS
    76.
    发明申请
    SYSTEM AND METHOD FOR TRACKING VEHICLES AND CONTAINERS 有权
    用于跟踪车辆和集装箱的系统和方法

    公开(公告)号：US20080191937A1

    公开(公告)日：2008-08-14

    申请号：US12028894

    申请日：2008-02-11

    申请人： David S. WISHERD ,  Robert W. Boyd ,  Tom Richardson ,  Santiago Romero ,  Michael A. Wohl

    发明人： David S. WISHERD ,  Robert W. Boyd ,  Tom Richardson ,  Santiago Romero ,  Michael A. Wohl

    IPC分类号： G01S5/14

    CPC分类号： G01S19/07 ,  G01S19/09

    摘要： A location system for tracking assets within a terminal includes a Differential Global Positioning System (DGPS) reference receiver within the terminal that receives GPS signals and generates DGPS correction data. In one aspect, a roving receiver unit is carried by an asset to be tracked within the terminal. It includes a GPS receiver that receives GPS signals and the DGPS correction data from the DGPS reference receiver. A tag transmitter transmits a wireless RF signal containing GPS location data based on received GPS signals and DGPS correction data. At least one access point is positioned within the terminal for receiving the wireless RF signal from the tag transmitter. A processor is operatively connected to the at least one access point for receiving GPS location data and determining a location of the asset to be tracked.

    摘要翻译： 用于跟踪终端内的资产的位置系统包括终端内的差分全球定位系统（DGPS）参考接收机，其接收GPS信号并产生DGPS校正数据。 在一个方面，粗纱接收机单元由在终端内跟踪的资产携带。 它包括GPS接收器，其接收来自DGPS参考接收机的GPS信号和DGPS校正数据。 标签发送器基于接收到的GPS信号和DGPS校正数据发送包含GPS位置数据的无线RF信号。 至少一个接入点位于终端内，用于从标签发射器接收无线RF信号。 处理器可操作地连接到所述至少一个接入点，用于接收GPS位置数据并确定要跟踪的资产的位置。

    Memory efficient LDPC decoding methods and apparatus
    77.
    发明授权
    Memory efficient LDPC decoding methods and apparatus 有权
    存储器高效的LDPC解码方法和装置

    公开(公告)号：US07127659B2

    公开(公告)日：2006-10-24

    申请号：US10909753

    申请日：2004-08-02

    申请人： Tom Richardson ,  Vladimir Novichkov

    发明人： Tom Richardson ,  Vladimir Novichkov

    IPC分类号： H03M13/00

    CPC分类号： H03M13/6362 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/1122 ,  H03M13/1137

    摘要： Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.

    摘要翻译： 描述了实现存储器高效LDPC解码的方法和装置。 根据本发明，消息信息以压缩状态存储以进行校验节点处理操作。 检查节点的状态被完全更新，然后进行提取处理，以生成可变节点消息的校验节点。 从可变节点接收的消息的符号可以由本发明的校验节点处理器模块存储以用于消息提取。 校验节点处理器可以以可变节点顺序处理消息，从而允许变量节点处理器和校验节点处理器以相同的顺序对消息进行操作，以减少或消除在校验节点和可变节点之间传递的消息的缓冲和/或重新排序的需要。 还描述了允许在先前的图形迭代完成之前在一个图形迭代上进行校验节点处理的图形结构。

    Methods and apparatus for reducing error floors in message passing decoders
    79.
    发明申请
    Methods and apparatus for reducing error floors in message passing decoders 有权
    消息传递解码器中减少错误层的方法和装置

    公开(公告)号：US20050138520A1

    公开(公告)日：2005-06-23

    申请号：US10892587

    申请日：2004-07-16

    申请人： Tom Richardson

    发明人： Tom Richardson

    IPC分类号： H03M13/03 ,  H03M13/11 ,  H03M13/29 ,  H04L1/00

    CPC分类号： H03M13/1128 ,  H03M13/1111 ,  H03M13/2963 ,  H03M13/3723 ,  H03M13/6331 ,  H04L1/0051 ,  H04L1/0057 ,  H04L25/03171

    摘要： An iterative message passing decoder, e.g., an LDPC decoder, operating in conjunction with a soft input-soft output signal processing unit, e.g., an ISI detector, has an error floor performance region influenced by the decoder's sub-optimal message passing nature. Error floor reduction is achieved by a simple message re-initialization mechanism. Decoder edge states, e.g., constraint to variable node messages in decoder memory, are reinitialized, e.g., for an iteration, during the decoding after soft values provided by signal processing unit have improved. During the message re-initialization and for some subsequent amount of iterative decoder processing, extrinsic information fed back from the decoder to the signal processing unit and/or soft values delivered to the decoder from the signal processing unit, in an outer communications loop, is temporarily frozen, e.g., using a switch and a buffer. Then, the outer communications loop is restored as the decoding continues, achieving improved decoding performance.

    摘要翻译： 与软输入软输出信号处理单元（例如ISI检测器）一起操作的迭代消息传递解码器（例如，LDPC解码器）具有受解码器的次优消息传递性质影响的错误楼层性能区域。 通过简单的消息重新初始化机制实现错误楼层减少。 解码器边缘状态，例如解码器存储器中对可变节点消息的约束，在由信号处理单元提供的软值改善之后，在解码期间被重新初始化，例如用于迭代。 在消息重新初始化期间和一些后续量的迭代解码器处理中，在外部通信环路中从解码器反馈到信号处理单元的外部信息和/或从信号处理单元递送到解码器的软值值是 暂时冻结，例如使用开关和缓冲器。 然后，随着解码的继续，恢复外部通信环路，实现改进的解码性能。