公开(公告)号：US08595569B2

公开(公告)日：2013-11-26

申请号：US12128516

申请日：2008-05-28

Applicant: Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

Inventor： Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

IPC: G06F11/00

CPC classification number: H04L1/0057 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6513 ,  H03M13/6516 ,  H04L1/0045

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

Abstract translation: 描述了一种灵活且相对硬件有效的LDPC解码器。 该解码器可以用低于用于控制解码过程的代码结构的完全并行性的并行级别来实现。 用于描述代码结构的相对简单的控制代码的每个命令可以被多次存储和执行以完成码字的解码。 使用相同的一组控制码指令支持不同的码字长度，但是根据码字长度，代码被实现不同的次数。 解码器可以通过简单地改变表示码字长度的代码提升因子而不需要改变存储的代码描述信息来切换不同长度的解码码字，并用于控制解码过程。 当解码短于最大支持码字长度的码字时，一些块存储位置可能不被使用。

公开(公告)号：US08533568B2

公开(公告)日：2013-09-10

申请号：US12050119

申请日：2008-03-17

Applicant: Tom Richardson ,  Hui Jin

Inventor： Tom Richardson ,  Hui Jin

IPC: G11C29/00

CPC classification number: H03M13/6508 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract translation: 描述了一种灵活且相对硬件高效的LDPC编码器。 编码器可以以小于平行度的水平来实现，该并行度小于用于控制编码过程的代码结构的完全并行性。 用于描述代码结构的相对简单的微代码的每个命令可以被多次存储和执行以完成代码字的编码。 可以使用相同的微代码指令集来支持不同的码字长度，但是根据所选择的使用的提升因子，代码被实现不同的次数。 LDPC编码器可以通过简单地改变用于控制编码处理的代码提升因子来切换不同长度的编码码字，而不需要改变存储的代码描述信息。 当编码比最大支持的码字长度短的码字时，一些块存储位置和/或寄存器可能不被使用。

公开(公告)号：US20070019583A1

公开(公告)日：2007-01-25

申请号：US11229019

申请日：2005-09-16

Applicant: Rajiv Laroia ,  Hui Jin ,  Junyi Li ,  Frank Lane ,  Tom Richardson

Inventor： Rajiv Laroia ,  Hui Jin ,  Junyi Li ,  Frank Lane ,  Tom Richardson

IPC: H04Q7/00

CPC classification number: H04L1/0025 ,  H04L1/0004 ,  H04L1/0005 ,  H04L1/0029 ,  H04L1/0039 ,  H04L1/0046 ,  H04L1/0057 ,  H04L1/0075 ,  H04L5/0053 ,  H04L27/0008 ,  H04L27/0012 ,  H04L27/2602 ,  H04L2001/0098

Abstract: Downlink traffic channel data rate options and methods of indicating to a wireless terminal a utilized downlink data rate option are described. The downlink traffic channel rate option for a segment is conveyed using an assignment signal and/or a block in the downlink traffic channel segment which is not used for user data. Downlink segment assignment signals in some implementations allocate fewer bits for rate option indication than are required to uniquely identify each option. In some implementations low rate options, e.g., using QPSK, are uniquely identified via assignment signals. Higher rate options, e.g., using QAM16 modulation, are conveyed via the distinct information block in the downlink traffic segment using a first coding/modulation method. Still higher rate options, e.g., using QAM16, QAM64, or QAM256, are conveyed via the information block in the segment using a second coding/modulation method which is applied to the rate option information.

Abstract translation: 下行业务信道数据速率选项和向无线终端指示使用的下行链路数据速率选项的方法进行描述。 使用未用于用户数据的下行链路业务信道段中的分配信号和/或块来传送段的下行业务信道速率选项。 在一些实现中的下行链路段分配信号比用于唯一地标识每个选项所需的比特率分配更少的比特选项指示。 在一些实现中，通过分配信号唯一地识别低速率选项，例如使用QPSK。 使用第一编码/调制方法，通过下行链路业务段中的不同信息块传送更高速率选项，例如使用QAM16调制。 使用应用于速率选项信息的第二编码/调制方法，通过片段中的信息块传送诸如使用QAM16，QAM64或QAM256的更高速率选项。

公开(公告)号：US08306541B2

公开(公告)日：2012-11-06

申请号：US11230331

申请日：2005-09-19

Applicant: Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

Inventor： Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

IPC: H04W72/00 ,  H04W4/00

CPC classification number: H04W28/22

Abstract: A wireless terminal receives an uplink traffic channel segment assignment including a maximum uplink rate option indicator. Each uplink rate option corresponds to a number of information bits, coding rate and modulation method. The maximum rate option indicator indicates the highest rate option that the wireless terminal is permitted to use when transmitting in the assigned traffic channel segment from the perspective of the base station. In some embodiments, the wireless terminal uses interference measurements to further quality, e.g., conditionally reduce, the maximum uplink rate option that may be used. Then, the wireless terminal selects an uplink rate option to use which is less than the determined allowed maximum uplink rate option, e.g., based on the amount of user data to communicate. The wireless terminal transmits data in the assigned uplink traffic channel segment in accordance with the wireless terminal selected uplink rate.

Abstract translation: 无线终端接收包括最大上行链路速率选项指示符的上行业务信道段分配。 每个上行速率选项对应于多个信息比特，编码率和调制方法。 最大速率选项指示符指示从基站的角度在从分配的业务信道段中发送时允许无线终端使用的最高速率选项。 在一些实施例中，无线终端使用干扰测量来进一步提高质量，例如有条件地减少可能使用的最大上行链路速率选项。 然后，无线终端例如基于要进行通信的用户数据量，选择所使用的上行链路速率选项小于所确定的允许的最大上行链路速率选项。 无线终端根据所选择的无线终端上行速率在所分配的上行业务信道段中发送数据。

公开(公告)号：US08196000B2

公开(公告)日：2012-06-05

申请号：US11761359

申请日：2007-06-11

Applicant: Hui Jin ,  Tom Richardson ,  Vladimir Novichkov

Inventor： Hui Jin ,  Tom Richardson ,  Vladimir Novichkov

IPC: H03M13/00

CPC classification number: H03M13/116 ,  H03M13/2757 ,  H03M13/2957 ,  H03M13/6331 ,  H04L1/0057 ,  H04L1/0071 ,  H04L25/03318

Abstract: A method, apparatus, and machine readable medium for processing a plurality of Z-vectors. Each Z-vector includes Z elements, and each element includes K bits. The Z-vectors correspond to a binary codeword, portions of which have a relationship to a plurality of transmission units. The Z-vectors are stored in a set of D memory arrays. Each memory array includes Z rows of memory locations. Each memory location corresponds to a different array column, and each array column corresponds to a different Z-vector. Each Z-vector identifies one column. A series of sets of control information is generated. Each set includes a transmission unit identifier, a Z-vector identifier, and a row identifier. For at least one set, P times K divided by D bits is read from each column identified by the Z-vector that is identified by the Z-vector identifier included in the set.

Abstract translation: 一种用于处理多个Z向量的方法，装置和机器可读介质。 每个Z向量包括Z个元素，每个元素包括K个比特。 Z向量对应于二进制码字，它们的一部分与多个传输单元有关系。 Z向量存储在一组D存储器阵列中。 每个存储器阵列包括Z行的存储器位置。 每个存储器位置对应于不同的阵列列，并且每个阵列列对应于不同的Z向量。 每个Z向量标识一列。 生成一系列控制信息。 每个集合包括传输单元标识符，Z向量标识符和行标识符。 对于至少一个集合，从被包括在集合中的Z向量标识符标识的Z向量所标识的每一行中读取P倍数K除以D比特。

公开(公告)号：US07706456B2

公开(公告)日：2010-04-27

申请号：US11370219

申请日：2006-03-07

Applicant: Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

Inventor： Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

IPC: H04K1/10

CPC classification number: H04L1/0028 ,  H04B14/026 ,  H04L1/0003 ,  H04L1/0007 ,  H04L1/0009 ,  H04L1/0025 ,  H04L1/0026 ,  H04L1/0033 ,  H04L5/023 ,  H04L5/04 ,  H04L27/0008 ,  H04L27/2604 ,  H04L27/3488 ,  Y02D50/10

Abstract: A stream of modulation symbols from a zero symbol rate (ZSR) coding/modulation module and a stream of modulation symbols from another type of coding/modulation module are input into an interweaver module. The interweaver module mixes the two input streams when assigning modulation symbols to be communicated in a segment. If a ZSR modulation symbol is non-zero, the ZSR modulation symbol is allocated a transmission position. If the ZSR modulation symbol is a zero modulation symbol, the modulation symbol from the other coding/modulation module is allocated the transmission position. The non-zero modulation symbols from the ZSR module are higher in power than the non-zero modulation symbols from the other module, thus facilitating detection and recovery.

Abstract translation: 来自零符号率（ZSR）编码/调制模块的调制符号流和来自另一种类型的编码/调制模块的调制符号流被输入到交织器模块中。 当分配要在段中传送的调制符号时，交织器模块混合两个输入流。 如果ZSR调制符号不为零，则ZSR调制符号被分配一个传输位置。 如果ZSR调制符号是零调制符号，则将来自另一个编码/调制模块的调制符号分配给发送位置。 来自ZSR模块的非零调制符号的功率高于来自另一个模块的非零调制符号，因此便于检测和恢复。

公开(公告)号：US20090063925A1

公开(公告)日：2009-03-05

申请号：US12128527

申请日：2008-05-28

Applicant: Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

Inventor： Tom Richardson ,  Hui Jin ,  Vladimir Novichkov

IPC: H03M13/05 ,  G06F11/07

CPC classification number: H04L1/0057 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/6513 ,  H03M13/6516 ,  H04L1/0045

Abstract: A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.

公开(公告)号：US20080163027A1

公开(公告)日：2008-07-03

申请号：US12050119

申请日：2008-03-17

Applicant: Tom Richardson ,  Hui Jin

Inventor： Tom Richardson ,  Hui Jin

IPC: H03M13/00

CPC classification number: H03M13/6508 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

Abstract: A flexible and relatively hardware efficient LDPC encoder is described. The encoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the encoding process. Each command of a relatively simple microcode used to describe the code structure can be stored and executed multiple times to complete the encoding of a codeword. Different codeword lengths can be supported using the same set of microcode instructions but with the code being implemented a different number of times depending on the lifting factor selected to be used. The LDPC encoder can switch between encoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor used to control the encoding processes. When coding codewords shorter than the maximum supported codeword length some block storage locations and/or registers may go unused.

Abstract translation: 描述了一种灵活且相对硬件高效的LDPC编码器。 编码器可以以小于平行度的水平来实现，该并行度小于用于控制编码过程的代码结构的完全并行性。 用于描述代码结构的相对简单的微代码的每个命令可以被多次存储和执行以完成代码字的编码。 可以使用相同的微代码指令集来支持不同的码字长度，但是根据所选择的使用的提升因子，代码被实现不同的次数。 LDPC编码器可以通过简单地改变用于控制编码处理的代码提升因子来切换不同长度的编码码字，而不需要改变存储的代码描述信息。 当编码比最大支持的码字长度短的码字时，一些块存储位置和/或寄存器可能不被使用。

公开(公告)号：US07231577B2

公开(公告)日：2007-06-12

申请号：US10635942

申请日：2003-08-07

Applicant: Tom Richardson ,  Vladimir Novichkov ,  Hui Jin

Inventor： Tom Richardson ,  Vladimir Novichkov ,  Hui Jin

IPC: H03M13/00

CPC classification number: H04L1/005 ,  H03M13/00 ,  H03M13/1102 ,  H03M13/296 ,  H03M13/3707 ,  H03M13/6325 ,  H03M13/658

Abstract: Methods and apparatus for scaling soft values as part of an error correction decoding process are described. Accurate decoding depends on use of the appropriate scale factor. Selection and use of the scale factor to scale soft values is designed to improve and/or optimize decoder performance without the need for prior knowledge of the correct scale factor or the actual channel conditions at the time the signal from which the soft values were obtained was transmitted through a communications channel. The techniques of the present invention assume that the soft values to be processed were transmitted through a communications channel having a quality that can be accurately described by a channel quality value. A scale factor is determined from the distribution of soft values to be scaled and an assumption that the channel through which they were transmitted was of the quality corresponding to a preselected channel quality value.

Abstract translation: 描述用于缩放软值作为纠错解码处理的一部分的方法和装置。 准确的解码取决于使用适当的比例因子。 设计用于缩放软值的比例因子的设计是为了提高和/或优化解码器性能，而不需要在获得软值的信号时获得正确比例因子或实际信道条件的先验知识 通过通信信道传输。 本发明的技术假设要通过具有可以通过信道质量值精确描述的质量的通信信道来发送待处理的软值。 根据要缩放的软值的分布确定比例因子，以及假设传输它们的信道具有与预先选择的信道质量值对应的质量。

公开(公告)号：US20060203713A1

公开(公告)日：2006-09-14

申请号：US11370204

申请日：2006-03-07

Applicant: Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

Inventor： Rajiv Laroia ,  Hui Jin ,  Tom Richardson ,  Junyi Li

IPC: H04J11/00

CPC classification number: H04L27/2601 ,  H04L5/023 ,  H04L25/49 ,  H04L25/4902 ,  H04L27/0008

Abstract: A device includes a zero symbol rate (ZSR) coding/modulation module and a second type coding/modulation module. Both modules generate modulation symbols to be conveyed using the same air link resources but with the non-zero ZSR symbols having a higher power level. The ZSR module generates a mixture of zero and non-zero modulation symbols. A ZSR modulation scheme communicates information using both the position of the non-zero modulation symbols and the phase and/or amplitude of the non-zero modulation symbols. Different ZSR schemes, implementing different ratios relating the number of zero symbols to the total number of symbols, can be associated with different low data rates while second module modulation schemes can be associated with different high data rates. Modulation symbols from two modules are in some embodiments, superimposed. In some embodiments, non-zero ZSR modulation symbols punch out second module modulation symbols which occupy the same air link resource.