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    Techniques for Connecting an External Network Coprocessor to a Network Processor Packet Parser
    71.
    发明申请
    Techniques for Connecting an External Network Coprocessor to a Network Processor Packet Parser 有权
    将外部网络协处理器连接到网络处理器数据包解析器的技术

    公开(公告)号：US20130308653A1

    公开(公告)日：2013-11-21

    申请号：US13884664

    申请日：2011-12-19

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-Jen Chang ,  Damon Philippe ,  Natarajan Vaidhyanathan ,  Colin B. Verrilli ,  Fabrice Jean Verplanken

    IPC分类号： H04L29/06

    CPC分类号： H04L29/0653 ,  G06F9/3877 ,  G06F9/544 ,  G06F13/385 ,  G06F15/163 ,  H04L69/22

    摘要： A network processor includes first communication protocol ports that each support ‘M’ minimum size packet data path traffic on ‘N’ lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=

    摘要翻译： 网络处理器包括第一通信协议端口，每个端口以“S”千兆位/秒（Gbps）在“N”通道上支持“M”个最小尺寸分组数据路径业务，并且在“n”个附加车道上以不同的通信协议单元的流量“ s Gbps 第一通信协议端口支持使用位于每个第一通信协议端口中的解析逻辑来访问外部协处理器。 解析逻辑在解析周期期间被配置为在接收到“M”大小的分组时向外部协处理器发送请求并且从外部协处理器接收响应。 解析逻辑在附加通道之一上向外部协处理器发送请求最大“m”字节字，并在附加通道之一上从外部协处理器接收响应最大“m”字节字，同时遵循等式 N×S / M =

    Host ethernet adapter for handling both endpoint and network node communications
    72.
    发明授权
    Host ethernet adapter for handling both endpoint and network node communications 失效
    主机以太网适配器，用于处理端点和网络节点通信

    公开(公告)号：US08576864B2

    公开(公告)日：2013-11-05

    申请号：US13011663

    申请日：2011-01-21

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

    IPC分类号： H04L12/28 ,  H04J1/16

    CPC分类号： G06F15/1735

    摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.

    摘要翻译： 提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。 所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。 该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序 所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务 模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

    Systems and methods for multi-frame control blocks
    78.
    发明授权
    Systems and methods for multi-frame control blocks 有权
    多帧控制块的系统和方法

    公开(公告)号：US07603539B2

    公开(公告)日：2009-10-13

    申请号：US12039304

    申请日：2008-02-28

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

    IPC分类号： G06F12/00

    CPC分类号： H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

    摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

    摘要翻译： 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

    Apparatus and method for efficiently modifying network data frames
    79.
    发明授权
    Apparatus and method for efficiently modifying network data frames 失效
    用于有效修改网络数据帧的装置和方法

    公开(公告)号：US07522621B2

    公开(公告)日：2009-04-21

    申请号：US11030344

    申请日：2005-01-06

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Fabrice J. Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9021

    摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.

    摘要翻译： 用于存储要修改的网络帧数据的装置和方法。 多个缓冲器存储布置在由帧控制块和缓冲器控制块所标识的数据结构中的网络数据。 与存储帧数据的每个缓冲器相关联的多个缓冲器控制块建立缓冲器的序列。 每个缓冲器控制块具有用于识别序列内的后续缓冲器的数据。 第一缓冲器由帧控制块的字段以及帧数据的开始和结束地址来标识。 可以通过改变缓冲器控制块和/或帧控制块内容而不将数据重写到存储器来修改帧数据，而不必复制或重写数据以便修改它。