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    Eliminating memory corruption when performing tree functions on multiple threads
    3.
    发明授权
    Eliminating memory corruption when performing tree functions on multiple threads 有权
    在多个线程上执行树函数时，消除内存损坏

    公开(公告)号：US07036125B2

    公开(公告)日：2006-04-25

    申请号：US10217529

    申请日：2002-08-13

    申请人： Claude Basso ,  Matthew William Kilpatrick Brown ,  Gordon Taylor Davis ,  Marco Heddes ,  Piyush Chunilal Patel ,  Grayson Warren Randall ,  Sonia Kiang Rovner ,  Colin Beaton Verrilli

    发明人： Claude Basso ,  Matthew William Kilpatrick Brown ,  Gordon Taylor Davis ,  Marco Heddes ,  Piyush Chunilal Patel ,  Grayson Warren Randall ,  Sonia Kiang Rovner ,  Colin Beaton Verrilli

    IPC分类号： G06F9/46 ,  G06F12/00

    CPC分类号： G06F9/52

    摘要： A method, system and computer program product for eliminating memory corruption when performing multi-threaded tree operations. A network processor may receive a command to perform a tree operation on a tree on one or more of multiple threads. Upon performing the requested tree operation, the network processor may lock one or more resources during a portion of the execution of the requested tree operation using one or more semaphores. A semaphore may refer to a flag used to indicate whether to “lock” or make available the resource associated with the semaphore. Locking may refer to preventing the resource from being available to other threads. Hence, by locking one or more resources during a portion of the tree operation, memory corruption may be eliminated in a multiple thread system while preventing these resources from being used by other threads for a minimal amount of time.

    摘要翻译： 一种用于在执行多线程树操作时消除内存损坏的方法，系统和计算机程序产品。 网络处理器可以在多个线程中的一个或多个上接收在树上执行树操作的命令。 在执行所请求的树操作时，网络处理器可以在使用一个或多个信号量的所请求的树操作的执行的一部分期间锁定一个或多个资源。 信号量可以指用于指示是否“锁定”或提供与信号量相关联的资源的标志。 锁定可能是指防止资源对其他线程可用。 因此，通过在树操作的一部分期间锁定一个或多个资源，可以在多线程系统中消除内存损坏，同时防止这些资源在最短时间内被其他线程使用。

    Method and system for efficient layer 3-layer 7 routing of internet protocol (“IP”) fragments
    4.
    发明授权
    Method and system for efficient layer 3-layer 7 routing of internet protocol (“IP”) fragments 有权
    网络协议（“IP”）片段的有效层3层7路由的方法和系统

    公开(公告)号：US07065086B2

    公开(公告)日：2006-06-20

    申请号：US09931206

    申请日：2001-08-16

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Philippe Damon ,  Gordon Taylor Davis

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Philippe Damon ,  Gordon Taylor Davis

    IPC分类号： H04L12/28

    CPC分类号： H04L49/25 ,  H04L49/602

    摘要： According to the present invention there is provided to a method and system for efficiently routing IP fragments (i.e., datagrams) at layer 3 through layer 7 of the OSI model without reassembling the fragments. Time-consuming reassembly of fragments of a datagram at higher layers that would be required via conventional methods is avoided, thereby improving processing speed of fragments and utilizing fewer resources for processing fragments of a datagram than would be required during reassembly of the fragments via conventional methods. The method and system route a datagram that has been fragmented into a plurality of fragments utilizing content-based routing information included in one or more fragments of the plurality of fragments, comprising: generating a context for the datagram associated with routing the plurality of fragments of the datagram and setting the context for the datagram to passive until content-based routing information included in the one or more fragments is received; caching received fragments while the context is set to passive; determining a destination for routing the plurality of fragments when content-based routing information included in the one or more fragments is received and setting the context for the datagram to active; and routing any cached fragments and subsequently received fragments of the datagram to the determined destination while the context is active without reassembling the plurality of fragments into the datagram. Additionally, a router and server load balancer incorporating the present invention are provided.

    摘要翻译： 根据本发明，提供了一种用于在不重新组装片段的情况下有效地路由OSI模型的层3到层7的IP片段（即，数据报）的方法和系统。 避免了通过常规方法需要的较高层数据报片段的重新组装，从而提高片段的处理速度，并利用较少的资源来处理数据报的片段，而不是通过常规方法重新组装片段时所需要的数据报片段 。 所述方法和系统使用包括在所述多个片段中的一个或多个片段中的基于内容的路由信息​​将已经被分段的数据报路由到多个片段中，包括：生成与路由多个片段的多个片段相关联的数据报的上下文 数据报并将数据报的上下文设置为被动，直到接收到包含在一个或多个片段中的基于内容的路由信息​​为止; 缓存接收到的片段，同时将上下文设置为被动; 当接收到包含在所述一个或多个片段中的基于内容的路由信息​​被接收并且将所述数据报的上下文设置为活动时，确定用于路由所述多个片段的目的地; 并且在上下文是活动的情况下将任何高速缓存的分段和随后接收的数据报的片段路由到所确定的目的地，而不将多个片段重新组合到数据报中。 另外，提供并入本发明的路由器和服务器负载均衡器。

    Packet classification using modified range labels
    5.
    发明授权
    Packet classification using modified range labels 失效
    数据包分类使用修改的范围标签

    公开(公告)号：US07796513B2

    公开(公告)日：2010-09-14

    申请号：US12187188

    申请日：2008-08-06

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

    IPC分类号： H04L12/26

    CPC分类号： H04L45/00 ,  H04L12/4625 ,  H04L45/54 ,  H04L45/7453 ,  H04L63/0263

    摘要： A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded to their respective significance. A range, based on a parameter in the packet header, is previously determined. Multiple rules are evaluated according to an overlapping of rules according to different ranges. Upon a determination that two or more rules overlap, each overlapping rule is expanded into multiple unique segments that identify unique range intersections. Each cluster of overlapping ranges is then offset so that at least one bit in a range for the rule remains unchanged. The range segments are then converted from binary to Gray code, which results in the ability to determine a CAM entry to use for each range.

    摘要翻译： 一种方法和系统，用于以分组分类密钥中的每个参数字段的一组范围标签进行编码，以便在分组分类器的最后处理阶段中优选地仅需要每个规则仅一个条目。 根据各自的意义对多个规则进行排序。 预先确定基于分组报头中的参数的范围。 根据不同范围的规则重叠来评估多个规则。 在确定两个或更多个规则重叠时，每个重叠规则被扩展为识别唯一范围交点的多个唯一段。 然后，每个重叠范围的簇被偏移，使得该规则的范围中的至少一个位保持不变。 范围段然后从二进制转换为格雷码，这导致确定每个范围使用的CAM条目的能力。

    Packet classification using modified range labels
    6.
    发明授权
    Packet classification using modified range labels 失效
    数据包分类使用修改的范围标签

    公开(公告)号：US07466687B2

    公开(公告)日：2008-12-16

    申请号：US10425097

    申请日：2003-04-28

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

    IPC分类号： H04L12/28

    CPC分类号： H04L45/00 ,  H04L12/4625 ,  H04L45/54 ,  H04L45/7453 ,  H04L63/0263

    摘要： A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded to their respective significance. A range, based on a parameter in the packet header, is previously determined. Multiple rules are evaluated according to an overlapping of rules according to different ranges. Upon a determination that two or more rules overlap, each overlapping rule is expanded into multiple unique segments that identify unique range intersections. Each cluster of overlapping ranges is then offset so that at least one bit in a range for the rule remains unchanged. The range segments are then converted from binary to Gray code, which results in the ability to determine a CAM entry to use for each range.

    摘要翻译： 一种方法和系统，用于以分组分类密钥中的每个参数字段的一组范围标签进行编码，以便在分组分类器的最后处理阶段中优选地仅需要每个规则仅一个条目。 根据各自的意义对多个规则进行排序。 预先确定基于分组报头中的参数的范围。 根据不同范围的规则重叠来评估多个规则。 在确定两个或更多个规则重叠时，每个重叠规则被扩展为识别唯一范围交点的多个唯一段。 然后，每个重叠范围的簇被偏移，使得该规则的范围中的至少一个位保持不变。 范围段然后从二进制转换为格雷码，这导致确定每个范围使用的CAM条目的能力。

    Controller for multiple instruction thread processors
    8.
    发明授权
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US08006244B2

    公开(公告)日：2011-08-23

    申请号：US10915983

    申请日：2004-08-11

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。

    Network processor which makes thread execution control decisions based on latency event lengths
    9.
    发明授权
    Network processor which makes thread execution control decisions based on latency event lengths 失效
    基于延迟事件长度的线程执行控制决策的网络处理器

    公开(公告)号：US07093109B1

    公开(公告)日：2006-08-15

    申请号：US09542189

    申请日：2000-04-04

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3851 ,  G06F9/3802

    摘要： A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable them to have rapid access to the shared memory. If execution of a thread becomes stalled due to a latency event, full control is granted to the next thread in the queue. The grant of control is temporary when a short latency event occurs or full when a long latency event occurs. Control is returned to the original thread when a short latency event is completed. Each execution thread utilizes an instruction prefetch buffer that collects instructions for idle execution threads when the instruction bandwidth is not fully utilized by an active execution thread. The thread execution control is governed by the collective functioning of a FIFO, an arbiter and a thread control state machine.

    摘要翻译： 在网络处理器和树形搜索协处理器之间建立一种控制机制来处理访问诸如以树结构格式化的信息的数据的延迟。 排队多个独立的指令执行线程使其能够快速访问共享存储器。 如果由于延迟事件导致线程执行失败，则会对队列中的下一个线程授予完全控制权。 当长时间延迟事件发生时，发生短延迟事件或满时，授权控制是暂时的。 当短暂延迟事件完成时，控制返回到原始线程。 每个执行线程使用指令预取缓冲器，当指令带宽未被活动执行线程充分利用时，该指令预取缓冲器收集空闲执行线程的指令。 线程执行控制由FIFO，仲裁器和线程控制状态机的集合功能决定。

    Controller for multiple instruction thread processors
    10.
    发明授权
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US06931641B1

    公开(公告)日：2005-08-16

    申请号：US09542206

    申请日：2000-04-04

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Fabrice Jean Verplanken

    IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16 ,  G06F9/00

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机构控制多线程处理器，使得当第一线程遇到延迟事件到第一预定义时间间隔时，临时控制在第一预定义时间间隔的持续时间内传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。