公开(公告)号：US20110188328A1

公开(公告)日：2011-08-04

申请号：US12699933

申请日：2010-02-04

申请人： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

发明人： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

IPC分类号： G11C7/00 ,  G11C8/16

CPC分类号： G11C8/16 ,  G11C11/412

摘要： A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.

摘要翻译： 多端口RAM电路具有耦合到多个位线和多个位线条的数据输入线。 电路也有多条字线。 存储单元耦合到位线，位线条和字线。 电路还包括控制器，使得字线能够基本上同时从位线写入存储单元。

公开(公告)号：US07872930B2

公开(公告)日：2011-01-18

申请号：US12121560

申请日：2008-05-15

申请人： Nan Chen ,  Sian-Yee Sean Lee ,  Seong-Ook Jung ,  Zhongze Wang

发明人： Nan Chen ,  Sian-Yee Sean Lee ,  Seong-Ook Jung ,  Zhongze Wang

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/10 ,  G11C29/12005

摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.

摘要翻译： 在第一电源电压电平下为存储器件设置电源电压。 响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。 响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。 响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。 响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。 响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。 响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

公开(公告)号：US20090285044A1

公开(公告)日：2009-11-19

申请号：US12121560

申请日：2008-05-15

申请人： Nan Chen ,  Sian-Yee Sean Lee ,  Seong-Ook Jung ,  Zhongze Wang

发明人： Nan Chen ,  Sian-Yee Sean Lee ,  Seong-Ook Jung ,  Zhongze Wang

IPC分类号： F21V29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/10 ,  G11C29/12005

摘要： A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level.

摘要翻译： 在第一电源电压电平下为存储器件设置电源电压。 响应于设置电源电压，以第一电源电压电平将测试数据写入存储器件。 响应于写入测试数据，存储器件的电源电压降低到低于第一电源电压电平的第二电源电压电平。 响应于降低电源电压，在第二电源电压电平下从存储器件读取测试数据。 响应于读取测试数据，存储器件的电源电压增加到高于第二电源电压电平的第三电源电压电平。 响应于增加电源电压，在第三电源电压电平下从存储器件读取测试数据。 响应于以第三电源电压从存储器件读取测试数据，将以第一电源电压电平写入存储器件的测试数据与从第三电源电压电平读出的测试数据进行比较。

公开(公告)号：US20070222002A1

公开(公告)日：2007-09-27

申请号：US11756922

申请日：2007-06-01

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L29/94

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/28194

摘要： A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion.

摘要翻译： 提供了一种用于在掺杂剂注入和激活之后使用氮注入和退火来减小栅极氧化物的有效厚度的方法。 更具体地说，本发明提供一种用于制造半导体器件的方法，例如晶体管，其包括硬化的栅极氧化物，其特征可以在多晶硅/栅极氧化物界面处具有相对较大的氮浓度， 栅极氧化物和栅极氧化物/衬底界面处。 另外，本发明提供了一种用于制造半导体器件的方法，该半导体器件具有设置在其多晶硅层上的金属栅极带（例如，金属硅化物层），该器件包括硬化的栅极氧化物，并且其特征可以是相对较大的氮 在硅化物/多晶硅界面处的浓度基本上防止交叉扩散。

公开(公告)号：US07119369B2

公开(公告)日：2006-10-10

申请号：US10758059

申请日：2004-01-15

申请人： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

发明人： Zhongze Wang ,  Chih-Chen Cho ,  Er-Xuan Ping

IPC分类号： H01L27/108

CPC分类号： H01L29/66651 ,  H01L21/76264 ,  H01L29/0653

摘要： A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

摘要翻译： 场效应晶体管具有体半导体衬底中的沟道区，沟道区的第一侧上的第一源极/漏极区，沟道区的第二侧上的第二源极/漏极区和外延的延伸 形成在体半导体衬底上以便从沟道区的每一侧延伸的单晶材料。

公开(公告)号：US07109105B2

公开(公告)日：2006-09-19

申请号：US10838587

申请日：2004-05-04

申请人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

发明人： Zhongze Wang ,  Michael P. Violette ,  Jigish Trivedi

IPC分类号： H01L21/8234 ,  H01L21/44

CPC分类号： H01L21/76888 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： Fuses for integrated circuits and semiconductor devices and methods for using the same. The semiconductor fuse contains two conductive layers, an overlying and underlying refractory metal nitride layer, on an insulating substrate. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure including the same materials. The fuse, which may be used to program redundant circuitry, may be blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

公开(公告)号：US06962841B2

公开(公告)日：2005-11-08

申请号：US10659081

申请日：2003-09-10

申请人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

发明人： John D. Trivedi ,  Zhongze Wang ,  Chih-Chen Cho ,  Mike Violette ,  Todd R. Abbott

IPC分类号： G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/412 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/11 ,  H01L27/1104

摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

公开(公告)号：US06900494B2

公开(公告)日：2005-05-31

申请号：US10780014

申请日：2004-02-17

申请人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

发明人： Todd R. Abbott ,  Mike Violette ,  Zhongze Wang ,  Jigish D. Trevidi

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： The method comprises forming a layer comprised of BPSG above a substrate and a plurality of transistors, forming a dielectric layer above the BPSG layer, the dielectric layer comprised of a material having a dielectric constant greater than approximately 6.0, forming a plurality of openings in the dielectric layer and the BPSG layer, each of the openings allowing contact to a doped region of one of the transistors, and forming a conductive local interconnect in each of the openings. In another embodiment, the method comprises forming a layer comprised of BPSG above the substrate and between the transistors, forming a local interconnect in openings formed in the BPSG layer, reducing a thickness of the BPSG layer after the local interconnects are formed, and forming a dielectric layer above the BPSG layer and between the local interconnects, wherein the dielectric layer has a dielectric constant greater than approximately 6.0.

摘要翻译： 该方法包括在衬底之上形成由BPSG组成的层和多个晶体管，在BPSG层上形成电介质层，介电层由介电常数大于约6.0的材料构成，在该介电层中形成多个开口 电介质层和BPSG层，每个开口允许接触晶体管之一的掺杂区域，并且在每个开口中形成导电局部互连。 在另一实施例中，该方法包括在衬底之上和晶体管之间形成由BPSG组成的层，在形成在BPSG层中的开口中形成局部互连，在局部互连形成之后减小BPSG层的厚度，并形成 电介质层在BPSG层之上和局部互连之间，其中介电层具有大于约6.0的介电常数。

公开(公告)号：US20050040463A1

公开(公告)日：2005-02-24

申请号：US10956196

申请日：2004-09-30

申请人： Zhongze Wang

发明人： Zhongze Wang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/78612

摘要： Source drain on insulator (SDOI) transistors and methods of forming SDOI transistors are described. The SDOI transistors are formed to provide electrical isolation between the body and the channel of the transistor. The electrical isolation comprises either a depletion layer or a p-n junction formed below the SDOI transistor channel region that spans laterally between the SDOI insulators.

摘要翻译： 描述了绝缘体源极漏极（SDOI）晶体管和形成SDOI晶体管的方法。 形成SDOI晶体管，以在主体和晶体管的通道之间提供电隔离。 电隔离包括在SDOI晶体管沟道区域之下形成的耗尽层或p-n结，跨越SDOI绝缘体之间的横向。

公开(公告)号：US06784062B2

公开(公告)日：2004-08-31

申请号：US10162289

申请日：2002-06-03

申请人： Chih-Chen Cho ,  Zhongze Wang

发明人： Chih-Chen Cho ,  Zhongze Wang

IPC分类号： H01L218238

CPC分类号： H01L27/11 ,  H01L21/82345 ,  H01L21/823842

摘要： A semiconductor fabrication method of forming a pair of transistor gates of opposite conductivity type by partially forming first and second gate stacks comprising an insulation layer, a conductive layer and polysilicon layer for the pair of transistor by removing a portion of the polysilicon layer. The polysilicon layer includes a dominant region of first-type conductive dopants and a dominant region of second-type conductive dopants. A first-type conductive transistor gate is formed by, completing the formation of the first gate stack and a second-type conductive transistor gate is formed by completing the formation of the second gate stack separately from the formation of the first-type transistor gate.

摘要翻译： 通过部分地形成第一和第二栅极堆叠来形成具有相反导电类型的一对晶体管栅极的半导体制造方法，该第一和第二栅极堆叠通过去除多晶硅层的一部分而包括一对晶体管的绝缘层，导电层和多晶硅层。 多晶硅层包括第一导电掺杂剂的主要区域和第二导电掺杂剂的主要区域。 通过完成第一栅极堆叠的形成而形成第一导电晶体管栅极，并且通过与第一型晶体管栅极的形成分开完成第二栅极堆叠的形成而形成第二导电晶体管栅极。