-
71.
公开(公告)号:US07706175B2
公开(公告)日:2010-04-27
申请号:US11839265
申请日:2007-08-15
申请人: Keiji Hosotani , Yoshiaki Asao , Akihiro Nitayama
发明人: Keiji Hosotani , Yoshiaki Asao , Akihiro Nitayama
IPC分类号: G11C11/00
CPC分类号: H01L27/228 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.
摘要翻译: 磁性随机存取存储器包括第一布线,形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件,以及 具有形成在固定层和记录层之间的固定层,记录层和非磁性层,形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层,形成第一侧绝缘膜 在金属层的侧表面,磁阻效应元件和第一布线,与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。
-
公开(公告)号:US20100097846A1
公开(公告)日:2010-04-22
申请号:US12563465
申请日:2009-09-21
CPC分类号: H01L27/228 , G11C11/161 , H01L43/12
摘要: A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an etching rate lower than an etching rate of each of the magnetic layers.
摘要翻译: 磁存储器包括设置在基板上的层间绝缘层,设置在层间绝缘层上的导电性底层,以及设置在下层上的磁阻元件,并且包括两个磁性层和介于该磁性层之间的非磁性层。 下层具有比每个磁性层的蚀刻速率低的蚀刻速率。
-
73.
公开(公告)号:US20100047930A1
公开(公告)日:2010-02-25
申请号:US12605072
申请日:2009-10-23
申请人: Keiji HOSOTANI , Yoshiaki Asao , Akihiro Nitayama
发明人: Keiji HOSOTANI , Yoshiaki Asao , Akihiro Nitayama
IPC分类号: H01L21/00
CPC分类号: H01L27/228 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.
摘要翻译: 磁性随机存取存储器包括第一布线,形成在第一布线上方并与第一布线间隔开的第二布线;形成在与第一布线的上表面接触形成的第一布线和第二布线之间的磁阻效应元件,以及 具有形成在固定层和记录层之间的固定层,记录层和非磁性层,形成在磁阻效应元件上并与磁阻效应元件集成以形成堆叠层的金属层,形成第一侧绝缘膜 在金属层的侧表面,磁阻效应元件和第一布线,与第一侧绝缘膜的侧表面接触形成的第一触点和形成在金属层上的第三布线和第一触点电连接 连接磁阻效应元件和第一触点。
-
74.
公开(公告)号:US20090296451A1
公开(公告)日:2009-12-03
申请号:US12406898
申请日:2009-03-18
申请人: Yoshiaki Asao
发明人: Yoshiaki Asao
IPC分类号: G11C11/00 , G11C11/416 , G11C7/00 , H01L29/66
CPC分类号: G11C13/0069 , G11C13/0002 , G11C13/0097 , G11C16/0466 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要: A resistance change memory includes a first interconnection, a second interconnection, a first resistance change element which has a first electrode, a second electrode, and a first tunnel insulating film provided between the first electrode and the second electrode, the first tunnel insulating film including a first trap region formed by introducing defects to trap holes or electrons, and the second electrode being connected to the first interconnection, and a first transistor whose current path has one end connected to the first electrode and the other end connected to the second interconnection.
摘要翻译: 电阻变化存储器包括第一互连,第二互连,第一电阻改变元件,其具有设置在第一电极和第二电极之间的第一电极,第二电极和第一隧道绝缘膜,第一隧道绝缘膜包括 通过引入缺陷以捕获空穴或电子而形成的第一陷阱区域,以及第二电极连接到第一互连件,以及第一晶体管,其电流通路的一端连接到第一电极,而另一端连接到第二互连。
-
公开(公告)号:US20090174007A1
公开(公告)日:2009-07-09
申请号:US12339814
申请日:2008-12-19
申请人: Jun NISHIMURA , Yoshiaki Asao
发明人: Jun NISHIMURA , Yoshiaki Asao
IPC分类号: H01L29/68
CPC分类号: H01L27/108 , H01L27/10802 , H01L29/7841
摘要: A semiconductor memory device comprising: a support substrate; an insulating film formed on the support substrate; a semiconductor film formed on the insulating film; a gate insulating film formed on the semiconductor film; a gate electrode film formed on the gate insulating film; and a source region and a drain region formed in the semiconductor film so as to sandwich the gate insulating film in a gate length direction, the source and drain regions contacting the insulating film at the bottom surface, and the semiconductor memory device storing data corresponding to the amount of charges accumulated in the semiconductor film surrounded by the insulating film, the gate insulating film, and the source and drain regions and electrically floated, wherein a border length between the source region and the gate insulating film contiguous to each other is different from a border length between the drain region and the gate insulating film to each other.
摘要翻译: 一种半导体存储器件,包括:支撑衬底; 形成在所述支撑基板上的绝缘膜; 形成在绝缘膜上的半导体膜; 形成在半导体膜上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极膜; 以及形成在所述半导体膜中的源极区域和漏极区域,以便在栅极长度方向夹着所述栅极绝缘膜,所述源极和漏极区域在所述底面处与所述绝缘膜接触,并且所述半导体存储器件存储对应于 在由绝缘膜,栅极绝缘膜以及源极和漏极区域包围的半导体膜中积累的电荷量被电浮动,其中源极区域和栅极绝缘膜彼此相邻的边界长度不同于 漏极区域和栅极绝缘膜之间的边界长度彼此。
-
公开(公告)号:US07505306B2
公开(公告)日:2009-03-17
申请号:US11609487
申请日:2006-12-12
IPC分类号: G11C11/00
CPC分类号: G11C11/16
摘要: A magnetic memory device includes a magnetization fixed layer provided above a semiconductor substrate surface and having a fixed magnetization direction. A first magnetization free layer is provided above the magnetization fixed layer, has variable magnetization direction, and has an easy magnetization axis extending along a plane intersecting the substrate surface and along a direction neither parallel nor perpendicular to the substrate surface. A second magnetization free layer is provided above the first magnetization free layer, has a magnetization that antiferromagnetically couples with the first magnetization free layer. A first write line is placed above and electrically connected to the second magnetization free layer, and extends in a direction that pierces the plane. A second write line faces the first and/or second magnetization free layer, and extends along the substrate surface and the plane and in a direction perpendicular to the first write line.
摘要翻译: 磁存储器件包括设置在半导体衬底表面上方并且具有固定的磁化方向的磁化固定层。 第一磁化自由层设置在磁化固定层的上方,具有可变的磁化方向,并且具有沿着与衬底表面相交的平面并且沿着不平行或垂直于衬底表面的方向延伸的易磁化轴。 第二磁化自由层设置在第一磁化自由层的上方,具有与第一磁化自由层反铁磁耦合的磁化。 第一写入线被放置在第二磁化自由层的上方并且电连接到第二写入线,并且沿着穿透该平面的方向延伸。 第二写入线面向第一和/或第二磁化自由层,并且沿着衬底表面和平面以及垂直于第一写入线的方向延伸。
-
公开(公告)号:US07414879B2
公开(公告)日:2008-08-19
申请号:US11313847
申请日:2005-12-22
申请人: Yoshiaki Asao , Akihiro Nitayama
发明人: Yoshiaki Asao , Akihiro Nitayama
IPC分类号: G11C11/00
CPC分类号: G11C11/16
摘要: A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.
摘要翻译: 半导体存储器件包括存储单元块,其包括串联连接在第一节点和第二节点之间的多个存储器单元,存储单元包括并联连接的磁阻元件和开关晶体管,磁阻元件是自旋注入 并且包括其磁化方向固定的固定层,其磁化方向改变的记录层和介于固定层和记录层之间的非磁性层,经由选择晶体管连接到第一结点的位线, 连接到开关晶体管的栅极的字线和连接到第二节点的写入线。
-
公开(公告)号:US20080035958A1
公开(公告)日:2008-02-14
申请号:US11833504
申请日:2007-08-03
申请人: Yoshiaki Asao
发明人: Yoshiaki Asao
IPC分类号: H01L29/82
CPC分类号: H01L27/228 , B82Y10/00
摘要: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in the substrate surface at roots on the first and second side surfaces of the first projection, first and second word lines formed above the semiconductor substrate, a bit line formed above the first and second word lines, a first magnetoresistive effect element formed between the bit line and the first word line, a second magnetoresistive effect element formed between the bit line and the second word line, a first contact which connects the first magnetoresistive effect element and the first drain diffusion layer, and a second contact which connects the second magnetoresistive effect element and the second drain diffusion layer.
摘要翻译: 磁性随机存取存储器包括:半导体衬底,具有从衬底表面突出的突出部,第一和第二栅电极以及形成在第一和第二侧表面上的第一源极扩散层和突起的上表面;第一和第二漏极扩散层 形成在第一突起的第一和第二侧表面上的根部处的基底表面上,形成在半导体衬底上方的第一和第二字线,形成在第一和第二字线上方的位线,形成在第一和第二字线之间的第一磁阻效应元件 位线和第一字线,形成在位线和第二字线之间的第二磁阻效应元件,连接第一磁阻效应元件和第一漏极扩散层的第一触点和连接第二磁阻的第二触点 效应元件和第二漏极扩散层。
-
公开(公告)号:US07092282B2
公开(公告)日:2006-08-15
申请号:US10638353
申请日:2003-08-12
申请人: Yoshiaki Asao
发明人: Yoshiaki Asao
IPC分类号: G11C11/00
CPC分类号: H01L27/222 , G11C11/15
摘要: A semiconductor integrated circuit device comprises magneto-resistive elements, bit lines electrically connected to the magneto-resistive elements at an end of the latter, read word lines electrically connected to the magneto-resistive elements at the other end of the latter and write word lines. The write word lines are insulated from the magneto-resistive elements and adapted to apply a magnetic field to selected magneto-resistive elements at the time of writing data to the selected magneto-resistive elements.
摘要翻译: 半导体集成电路器件包括磁阻元件,位于后端的电阻元件电连接的位线,在后者的另一端电连接到磁阻元件的读字线和写字线 。 写字线与磁阻元件绝缘,并且适于在将数据写入所选择的磁阻元件时将磁场施加到所选择的磁阻元件。
-
公开(公告)号:US07064402B2
公开(公告)日:2006-06-20
申请号:US11189851
申请日:2005-07-27
申请人: Takeshi Kajiyama , Tomomasa Ueda , Tatsuya Kishi , Hisanori Aikawa , Masatoshi Yoshikawa , Yoshiaki Asao , Hiroaki Yoda
发明人: Takeshi Kajiyama , Tomomasa Ueda , Tatsuya Kishi , Hisanori Aikawa , Masatoshi Yoshikawa , Yoshiaki Asao , Hiroaki Yoda
IPC分类号: H01L29/82
CPC分类号: G11C11/16 , B82Y10/00 , H01L27/228 , H01L43/08 , H01L43/12
摘要: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.
-
-
-
-
-
-
-
-
-