公开(公告)号：US07664040B2

公开(公告)日：2010-02-16

申请号：US11670873

申请日：2007-02-02

Applicant: Cedell A. Alexander, Jr.

Inventor： Cedell A. Alexander, Jr.

IPC: H04L12/28

CPC classification number: H04L45/742 ,  H04L45/12 ,  H04L45/122 ,  H04L45/46

Abstract: The solution to the shortest path between a source node and multiple destination nodes is accelerated using a grouping of nodes, where the nodes are grouped based on distance from the source node, and a corresponding set of memory locations that indicate when a group includes one or more nodes. The memory locations can be quickly searched to determine the group that represents the shortest distance from the source node and that includes one or more nodes. Nodes may be grouped into additional groupings that do not correspond to the set of memory locations, when the distance from the source node to the nodes exceeds the range of memory locations. Advantageously, the disclosed system and method provide the ability to reach asymptotically optimal performance.

Abstract translation: 使用一组节点来加速在源节点和多个目的地节点之间的最短路径的解决方案，其中根据与源节点的距离对节点进行分组，以及相应的一组存储器位置，其指示组何时包括一个或 更多的节点。 可以快速搜索存储器位置以确定代表距离源节点的最短距离并且包括一个或多个节点的组。 当从源节点到节点的距离超过存储器位置的范围时，节点可以被分组成不对应于该组存储器位置的附加分组。 有利地，所公开的系统和方法提供达到渐近最佳性能的能力。

公开(公告)号：US07643504B2

公开(公告)日：2010-01-05

申请号：US11605790

申请日：2006-11-29

Applicant: Yair Hadas ,  Avraham Shalev

Inventor： Yair Hadas ,  Avraham Shalev

IPC: H04L12/56

CPC classification number: H04L47/10 ,  H04L47/283 ,  H04L47/39

Abstract: A system and method are provided for controlling information flow from a channel service module (CSM) in an asymmetric channel environment. The method provides information for transmission to an OSI model PHY (physical) layer device with a channel buffer. The PHY device channel buffer current capacity is estimated. Information is sent to the channel buffer responsive to estimating the channel buffer capacity, prior to receiving a Polling Result message from the PHY device. Initially, Polling Request messages are sent to the PHY device, and Polling Result messages received from the PHY device, as is conventional. In response to analyzing the Polling messages, a transmission pattern is determined, which includes the amount of information to transmit and a period between transmissions.

Abstract translation: 提供了一种用于控制来自不对称信道环境中的信道服务模块（CSM）的信息流的系统和方法。 该方法提供用于传输到具有信道缓冲器的OSI模型PHY（物理）层设备的信息。 估计PHY设备通道缓冲区电流容量。 在从PHY设备接收到轮询结果消息之前，响应于估计信道缓冲器容量，将信息发送到信道缓冲器。 最初，轮询请求消息被发送到PHY设备，以及从PHY设备接收的轮询结果消息，如传统的。 响应于分析轮询消息，确定传输模式，其包括要发送的信息量和传输之间的周期。

公开(公告)号：US07603044B1

公开(公告)日：2009-10-13

申请号：US12327753

申请日：2008-12-03

Applicant: Keith Conroy ,  Omer Acikel

Inventor： Keith Conroy ,  Omer Acikel

IPC: H04B10/06

CPC classification number: H04B10/69 ,  H04B10/0795 ,  H04B10/671 ,  H04J14/06

Abstract: A system and method are provided for calibrating orthogonal polarity in a multichannel optical transport network (OTN) receiver. The method accepts a composite signal and separates the polarization of the signal into a pair of 2n-phase shift keying (2n-PSK) modulated input signals via Ix and Qx optical signal paths, where n≧1. Likewise, a pair of 2p-PSK modulated input signals are accepted via Iy and Qy optical signal paths where p≧1. Polarization-adjusted I′x, Q′x, I′y, and Q′y signals are generated. An average magnitude is compared to either 2×the absolute magnitude of (I′x and Q′x), or 2×the absolute magnitude of (I′y and Q′y). The average magnitude value can be used that is either 2×(a predetermined peak signal amplitude), or the sum of the absolute magnitudes of (I′x and Q′x) and (I′y and Q′y). The polarization-adjusted I′x, Q′x, I′y, and Q′y signals are modified until the magnitude comparison is about zero.

Abstract translation: 提供了一种在多通道光传送网（OTN）接收机中校准正交极性的系统和方法。 该方法接受复合信号，并通过Ix和Qx光信号路径将信号的极化分离成一对2n相移键控（2n-PSK）调制输入信号，其中n> = 1。 同样，一对2p-PSK调制输入信号通过I>和Qy光信号路径接受，其中p> = 1。 产生极化调整的I'x，Q'x，I'y和Q'y信号。 将平均幅度与（I'x和Q'x）的绝对幅度相比，或（I'y和Q'y）的绝对值的2倍。 可以使用平均幅度值，其为2x（预定峰值信号幅度）或绝对值（I'x和Q'x）和（I'y和Q'y）之和。 经偏振调整的I'x，Q'x，I'y和Q'y信号被修改，直到幅度比较为零为止。

公开(公告)号：US07583709B2

公开(公告)日：2009-09-01

申请号：US11368573

申请日：2006-03-06

Applicant: Dimitrios Giannakopoulos

Inventor： Dimitrios Giannakopoulos

IPC: H04J3/02

CPC classification number: H04L7/0008

Abstract: A system and method are provided for transporting Plesiochronous Digital Hierarchy (PDH) tributaries. The method accepts a plurality of PDH tributaries; generates a serial data stream of interleaved PDH tributaries; generates a serial control stream of signals for recovering the PDH tributaries; and, generates a clock signal for timing the data and control streams. The serial data stream of interleaved PDH tributaries is loaded into the payload of a data frame structure. Likewise, the serial control stream is loaded into the payload of a control frame structure. The data bytes of the serial data stream and the control bytes of the serial control stream are both transmitted at the same data rate. That is, there is a control byte generated for each data byte. Thus, the control bytes in the control frame structure are aligned with corresponding data bytes in the data frame structure.

Abstract translation: 提供了一种用于传输分时数字体系（PDH）支流的系统和方法。 该方法接受多个PDH支路; 生成交错PDH支路的串行数据流; 生成用于恢复PDH支流的串行控制信号流; 并且产生用于定时数据和控制流的时钟信号。 交错PDH支路的串行数据流被加载到数据帧结构的有效载荷中。 类似地，串行控制流被加载到控制帧结构的有效载荷中。 串行数据流的数据字节和串行控制流的控制字节都以相同的数据速率传输。 也就是说，每个数据字节都有一个控制字节。 因此，控制帧结构中的控制字节与数据帧结构中的相应数据字节对齐。

公开(公告)号：US07512150B2

公开(公告)日：2009-03-31

申请号：US10395843

申请日：2003-03-24

Applicant: Timothy P. Walker ,  Jay Quirk

Inventor： Timothy P. Walker ,  Jay Quirk

IPC: H04J3/16

CPC classification number: H04J3/1658 ,  H04J2203/0085 ,  H04J2203/0089

Abstract: A high-capacity digital communications system and method of transporting 10 GbE LAN packets between user devices over an OTN network that allows the packets to be transported in a manner that is transparent to the destination device(s) on the network. The digital communications system includes an OTN network, and at least one source device and at least one destination device connected to the network via respective 10 Gbase-R interfaces. The system transports 10 GbE LAN data packets over the OTN network by performing decoding on the packets to recover the preamble and variable length data contained in each packet, removing the IPG between successive packets in the stream, encapsulating the packets including the respective preambles and data, and mapping the encapsulated packets to the overhead and payload areas of ODUk frames. The packets are then transported over the OTN network from the source device to the destination device.

Abstract translation: 一种高容量数字通信系统和方法，其通过OTN网络在用户设备之间传输10GbE LAN分组，其允许以对网络上的目的地设备是透明的方式传送分组。 数字通信系统包括OTN网络，以及至少一个源设备和经由相应的10个Gbase-R接口连接到该网络的至少一个目的设备。 该系统通过OTN网络传输10GbE LAN数据包，对数据包执行解码，以恢复每个数据包中包含的前同步码和可变长度数据，从而消除数据流中连续数据包之间的IPG，封装包括各自的前导码和数据的数据包 ，并将封装的分组映射到ODUk帧的开销和有效载荷区域。 分组然后通过OTN网络从源设备传输到目的设备。

公开(公告)号：US07492763B1

公开(公告)日：2009-02-17

申请号：US10893117

申请日：2004-07-16

Applicant: Cedell A. Alexander, Jr.

Inventor： Cedell A. Alexander, Jr.

IPC: H04L12/56

CPC classification number: H04L49/351 ,  H04L12/4645 ,  H04L47/10 ,  H04L49/3009 ,  H04L49/354 ,  Y10S707/99936

Abstract: An integrated circuit has a hardware decoder that parses a frame to identify a type of encapsulation. The integrated circuit also has a number of hardware parsers, each parser being coupled to the decoder by an enable line. During packet processing, one of the parsers is enabled by the decoder, based on the value which identifies the encapsulation type. The enabled parser retrieves one or more attributes from the frame, depending on the encapsulation. The integrated circuit also has a register, coupled to each parser, to hold the attributes. The integrated circuit also has a key generation hardware which creates a key, by concatenating from the attributes register, certain attributes that are pre-selected by a user for forming the key. The integrated circuit uses the key to look up in memory a set of user-specified actions that are then performed on data in the frame.

Abstract translation: 集成电路具有解析帧以识别封装类型的硬件解码器。 集成电路还具有多个硬件解析器，每个解析器通过使能线耦合到解码器。 在分组处理期间，解码器之一基于识别封装类型的值，由解码器使能。 启用的解析器取决于封装，从帧中检索一个或多个属性。 集成电路还具有耦合到每个解析器的寄存器，以保持属性。 集成电路还具有密钥生成硬件，其通过从属性寄存器连接由用户预先选择的用于形成密钥的某些属性来创建密钥。 集成电路使用密钥在内存中查找一组用户指定的动作，然后对帧中的数据执行。

公开(公告)号：US07457390B2

公开(公告)日：2008-11-25

申请号：US11541176

申请日：2006-09-29

Applicant: Jeffrey W. Spires ,  Ravi Subrahmanyan

Inventor： Jeffrey W. Spires ,  Ravi Subrahmanyan

IPC: H04L25/00

CPC classification number: H04J3/076

Abstract: A timeshared data tributary mapping system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries and stores current buffer-fill information at a rate of about one tributary per Fsys clock cycle. An accumulation of buffer-fill information for the plurality of tributaries is updated with current buffer-fill information every Fsys clock cycle. The accumulation of buffer-fill information for the plurality of tributaries is sampled at a sample rate frequency (Fsample), where Fsample

Abstract translation: 提供了一种分时数据支配映射系统和方法，用于将信息映射到同步有效载荷信封（SPE）。 该方法缓冲来自多个支路的数据，并以每Fsys时钟周期大约一个支路的速率存储当前缓冲器填充信息。 每个Fsys时钟周期，使用当前缓冲器填充信息来更新多个支路的缓冲器填充信息的累加。 以采样率频率（Fsample）对多个支流的缓冲器填充信息的累积进行采样，其中Fsample

公开(公告)号：US07440533B2

公开(公告)日：2008-10-21

申请号：US11648920

申请日：2007-01-03

Applicant: Jeffrey W. Spires ,  Ravi Subrahmanyan

Inventor： Jeffrey W. Spires ,  Ravi Subrahmanyan

IPC: H04L25/00 ,  H04J3/07

CPC classification number: H04J3/076

Abstract: A system and modulation method are provided for reducing jitter in the mapping of information into Synchronous Payload Envelopes (SPEs), in a data tributary mapping system. The method comprises buffering data from a plurality of tributaries, and generating buffer-fill information responsive to the buffered data being written and read. The buffer-fill information is filtered, producing rate control information. The rate control information is modulated, and the modulated rate control information is used in controlling the mapping of buffered tributaries into a SPE. The rate control information can be modulated with periodic signals, such as a sine or square wave, and pseudorandom signals with an average value of about zero.

Abstract translation: 提供了一种系统和调制方法，用于在数据支路映射系统中减少信息映射到同步有效载荷包络（SPE）中的抖动。 该方法包括缓冲来自多个支路的数据，以及响应于正被写入和读取的缓冲数据产生缓冲器填充信息。 缓冲填充信息被过滤，产生速率控制信息。 速率控制信息被调制，并且调制速率控制信息用于控制缓冲支路到SPE的映射。 速率控制信息可以用诸如正弦波或方波的周期信号和平均值约为零的伪随机信号进行调制。

公开(公告)号：US20080229012A1

公开(公告)日：2008-09-18

申请号：US11717318

申请日：2007-03-13

Applicant: Christophe Therene ,  James R. Schmidt

Inventor： Christophe Therene ,  James R. Schmidt

IPC: G06F12/00

CPC classification number: G06F11/1076 ,  G06F2211/1057 ,  G06F2211/1059

Abstract: A system and method are provided for efficiently initializing a redundant array of independent disks (RAID). The method monitors host write operations and uses that information to select the optimal method to perform a parity reconstruction operation. The bins to which data access write operations have not occurred can be initialized using a zeroing process. In one aspect, the method identifies drives in the RAID array capable of receiving a ‘WriteRepeatedly’ command and leverages that capability to eliminate the need for the RAID disk array controller to provide initialization data for all disk array initialization transfers. This reduces the RAID array controller processor and I/O bandwidth required to initialize the array and further reduces the time to initialize a RAID array. In a different aspect, a method is provided for efficiently selecting a host write process for optimal data redundancy and performance in a RAID array.

Abstract translation: 提供了一种用于有效初始化独立磁盘冗余阵列（RAID）的系统和方法。 该方法监视主机写入操作，并使用该信息来选择执行奇偶校验重建操作的最佳方法。 数据访问写入操作未发生的存储区可以使用归零过程进行初始化。 在一个方面，该方法识别能够接收“WriteRepeatedly”命令的RAID阵列中的驱动器，并利用该功能来消除RAID磁盘阵列控制器为所有磁盘阵列初始化传输提供初始化数据的需要。 这可以减少RAID阵列控制器处理器和初始化阵列所需的I / O带宽，并进一步减少初始化RAID阵列的时间。 在不同的方面，提供了一种用于有效地选择主机写入过程以优化RAID阵列中的数据冗余和性能的方法。

公开(公告)号：US07424496B1

公开(公告)日：2008-09-09

申请号：US10103415

申请日：2002-03-20

Applicant: Ilan Pardo

Inventor： Ilan Pardo

IPC: G06F17/30

CPC classification number: G06F9/30101 ,  G06F9/526 ,  Y10S707/99942 ,  Y10S707/99952 ,  Y10S707/99955

Abstract: Prior to updating a database entry, an update task invalidates a valid indicator (e.g., a bit) associated with the database entry. The update task waits for any other tasks (e.g., user tasks) that are accessing the database entry to complete their processing. In particular, a synchronization register holds a synchronization entry (e.g., a bit) for each user task that is created by a micro controller. The update task sets each synchronization entry of the synchronization register to a first value. As each user task completes its processing, the synchronization entry associated with the user task in the synchronization register is set to a second value (e.g., the synchronization bit is reset). The update task monitors the synchronization register, and, when each synchronization entry has been set to the second value, the update task performs its update of the database entry.

Abstract translation: 在更新数据库条目之前，更新任务使与数据库条目相关联的有效指示符（例如，位）无效。 更新任务等待访问数据库条目以完成其处理的任何其他任务（例如，用户任务）。 特别地，同步寄存器保存由微控制器创建的每个用户任务的同步条目（例如，位）。 更新任务将同步寄存器的每个同步条目设置为第一个值。 当每个用户任务完成其处理时，与同步寄存器中的用户任务相关联的同步条目被设置为第二值（例如，同步位被复位）。 更新任务监视同步寄存器，并且当每个同步条目被设置为第二个值时，更新任务执行数据库条目的更新。