公开(公告)号：US09140733B2

公开(公告)日：2015-09-22

申请号：US13579249

申请日：2011-02-18

Applicant: Edgar Schmidhammer ,  Veit Meister ,  Gerhard Zeller

Inventor： Edgar Schmidhammer ,  Veit Meister ,  Gerhard Zeller

IPC: G06G7/12 ,  G01R27/06

CPC classification number: G01R27/06

Abstract: A detector circuit can be used for determining the reflection coefficients of HF signals in a signal path. The detector circuit includes a bidirectional hybrid coupler, logarithmic amplifiers connected to the hybrid couple, and a subtractor having an offset connection.

Abstract translation: 检测器电路可用于确定信号路径中HF信号的反射系数。 检测器电路包括双向混合耦合器，连接到混合耦合的对数放大器和具有偏移连接的减法器。

公开(公告)号：US09104973B2

公开(公告)日：2015-08-11

申请号：US13239123

申请日：2011-09-21

Applicant: Eugene M. Izhikevich ,  Botond Szatmary ,  Csaba Petre ,  Jayram Moorkanikara Nageswaran ,  Filip Piekniewski

Inventor： Eugene M. Izhikevich ,  Botond Szatmary ,  Csaba Petre ,  Jayram Moorkanikara Nageswaran ,  Filip Piekniewski

IPC: G06N3/04 ,  G06N3/063 ,  G06N99/00

CPC classification number: G06N3/049 ,  G06N3/0454 ,  G06N3/063 ,  G06N99/007

Abstract: A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Neuronal network and methods for operating neuronal networks comprise a plurality of units, where each unit has a memory and a plurality of doublets, each doublet being connected to a pair of the plurality of units. Execution of unit update rules for the plurality of units is order-independent and execution of doublet event rules for the plurality of doublets is order-independent.

Abstract translation: 公开了一种简单的格式，并被称为基本网络描述（END）。 该格式可以充分描述大规模神经元模型和软件或硬件引擎的实施例，以有效地模拟这种模型。 这种神经形态发动机的架构对于具有尖峰时间依赖可塑性的加标网络的高性能并行处理是最佳的。 用于操作神经元网络的神经元网络和方法包括多个单元，其中每个单元具有存储器和多个双重元件，每个双引脚连接到一对多个单元。 多个单元的单元更新规则的执行是与订单无关的，并且用于多个双工的双重事件规则的执行是与订单无关的。

公开(公告)号：US09098153B2

公开(公告)日：2015-08-04

申请号：US13571765

申请日：2012-08-10

Applicant: Guozhong Shen ,  Ozan E. Erdogan

Inventor： Guozhong Shen ,  Ozan E. Erdogan

IPC: G06F3/045 ,  G06F3/041 ,  G06F3/044

CPC classification number: G06F3/044 ,  G06F3/041 ,  G06F3/0416 ,  G06F3/045

Abstract: A capacitive touch panel may include a driver and a drive electrode configured to be connected to the driver. The driver is configured to power the drive electrode with a drive signal having a first signal characteristic during a first time interval, and a second signal characteristic different from the first signal characteristic during a second time interval subsequent to the first time interval. The first signal characteristic may comprise one or more of a first frequency, a first phase, or a first amplitude during the first time interval, and the second signal characteristic may comprise one or more of a second frequency, a second phase, or a second amplitude, where one or more of the first frequency, first phase, or first amplitude may be different from one or more of the second frequency, second phase, or second amplitude, respectively.

Abstract translation: 电容式触摸面板可以包括被配置为连接到驱动器的驱动器和驱动电极。 驱动器被配置为在第一时间间隔期间具有第一信号特性的驱动信号和在第一时间间隔之后的第二时间间隔期间与第一信号特性不同的第二信号特性为驱动电极供电。 第一信号特征可以在第一时间间隔期间包括第一频率，第一相位或第一幅度中的一个或多个，并且第二信号特征可以包括第二频率，第二相位或第二频率中的一个或多个 幅度，其中第一频率，第一相位或第一幅度中的一个或多个可以分别与第二频率，第二相位或第二幅度中的一个或多个不同。

公开(公告)号：US09069912B2

公开(公告)日：2015-06-30

申请号：US13436944

申请日：2012-03-31

Applicant: Philippe Boucard ,  Jean-Jacques Lecler

Inventor： Philippe Boucard ,  Jean-Jacques Lecler

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/22

CPC classification number: G06F13/4059 ,  G06F13/22 ,  G06F13/4031

Abstract: A Network-on-Chip (NoC) is provided that performs reordering of transaction responses such as those with requests that cross address mapping boundaries. Ordering is ensured by filtering logic in reorder buffers, some of which include storage to allow multiple simultaneously pending transactions. Transactions are transported by a packet-based transport protocol. The reorder buffering is done at packet level, within the transport topology. Reorder buffers are distributed physically throughout the floorplan of the chip, they have localized connectivity to initiators, and they operate in separate power and clock domains.

Abstract translation: 提供了片上网络（NoC），其执行诸如具有跨地址映射边界的请求的事务响应的重新排序。 通过在重排序缓冲区中过滤逻辑来确保排序，其中一些包括存储以允许多个同时挂起的事务。 事务通过基于分组的传输协议传送。 重新排序缓冲在传输拓扑中的分组级完成。 重新排序缓冲区物理地分布在芯片的整个平面图中，它们具有到启动器的本地化连接，并且它们在单独的电源和时钟域中操作。

公开(公告)号：US08965046B2

公开(公告)日：2015-02-24

申请号：US13423039

申请日：2012-03-16

Applicant: Ben-Zion Shaick

Inventor： Ben-Zion Shaick

IPC: G06K9/62

CPC classification number: G06K9/00302 ,  G06K9/00261 ,  G06K9/00268 ,  G06K9/00308 ,  G06K9/00624 ,  G06K9/52 ,  G06K9/6267 ,  G06K9/6857 ,  G06T7/20 ,  G06T2207/20081 ,  G06T2207/30201

Abstract: A method, apparatus, and manufacture for smiling face detection is provided. For each frame, a list of new smiling faces for the frame is generated by performing smiling face detection employing an object classifier that trained is to distinguish between smiling faces and all objects in the frame that are not smiling faces. For the first frame, the list of new smiling faces is employed as an input smiling face list for the next frame. For each frame after the first frame, a list of tracked smiles for the frame is generated by tracking smiling faces in the frame from the input smiling list for the frame. Further, a list of new smiling faces is generated for the next frame by combining the list of new smiling faces for the frame with the list of tracked smiles for the frame.

Abstract translation: 提供了一种用于微笑脸部检测的方法，装置和制造。 对于每个帧，通过使用被训练来区分微笑面部和不是笑脸的帧中的所有对象的对象分类器，通过执行微笑脸部检测来生成框架的新的笑脸的列表。 对于第一帧，新的笑脸的列表被用作下一帧的输入笑脸列表。 对于第一帧之后的每帧，通过从帧的输入微笑列表中跟踪帧中的笑脸来生成帧的跟踪微笑的列表。 此外，通过将用于该帧的新的笑脸的列表与用于该帧的被跟踪的微笑的列表相组合，为下一帧生成新的笑脸的列表。

公开(公告)号：US08793644B2

公开(公告)日：2014-07-29

申请号：US13487087

申请日：2012-06-01

Applicant: Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

Inventor： Daniel Michel ,  Xavier Van Ruymbeke ,  Pascal Godet ,  Xavier Leloup

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/505 ,  G06F2217/84

Abstract: A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.

Abstract translation: 公开了一种方法和NoC设计工具，其将定时报告中列出的路径和区域报告中的单位大小自动映射到NoC的拓扑，并在GUI中显示路径和单位大小。 该工具还可以自动添加流水线阶段，由时间预算允许的最大延迟分隔，以便以自动方式实现时序收敛。

公开(公告)号：US08766741B2

公开(公告)日：2014-07-01

申请号：US12687559

申请日：2010-01-14

Applicant: Edgar Schmidhammer

Inventor： Edgar Schmidhammer

IPC: H03H7/38 ,  H01G7/06

CPC classification number: H03J3/185 ,  H01G7/06 ,  H03H7/38

Abstract: A circuit is proposed by means of which a ceramic component having two electrodes can be provided with a uniform, but periodically alternating BIAS voltage. The component has properties dependent on the level of the BIAS voltage and, for the purpose of an increased service life, is connected to a generator for generating a BIAS voltage and to means for periodically reversing the polarity of the BIAS voltage present at the electrodes. In a method for operating the component having variable properties, a uniform BIAS voltage, the polarity of which is periodically reversed, however, is applied to the electrodes, and the service life of the component is thus increased.

Abstract translation: 提出了一种电路，通过该电路可以提供具有两个电极的陶瓷部件，其具有均匀但周期性交替的BIAS电压。 该组件具有取决于BIAS电压的水平的性质，并且为了增加的使用寿命，连接到用于产生BIAS电压的发电机，并且用于周期性地反转存在于电极处的BIAS电压的极性的装置。 在用于操作具有可变特性的部件的方法中，将均匀的BIAS电压（其极性周期性地反转）施加到电极上，从而增加了部件的使用寿命。

公开(公告)号：US08645557B2

公开(公告)日：2014-02-04

申请号：US11482175

申请日：2006-07-06

Applicant: Cesar Douady ,  Philippe Boucard

Inventor： Cesar Douady ,  Philippe Boucard

IPC: G06F15/16

CPC classification number: H04L12/66 ,  G06F13/4022

Abstract: The system of interconnections (20) for external functional blocks on a chip provided with a single configurable communication protocol, comprises two physically separate communication networks (21, 22): a request network (21) for transmitting request messages from an initiating block (23, 24, 25, 26) to a recipient block (27, 28, 29, 30, 31) and a response network (22) for transmitting response messages from a recipient block (27, 28, 29, 30, 31) to an initiating block (23, 25, 26). The response messages include additional information making said request (21) and response (22) networks able to respectively manage the request messages and the response messages independently.

Abstract translation: 用于设置有单个可配置通信协议的芯片上的外部功能块的互连系统（20）包括两个物理上分离的通信网络（21,22）：用于从启动块（23）发送请求消息的请求网络（21） ，24,25,26）发送到接收方块（27,28,29,30,31）和响应网络（22），用于将接收方块（27,28,29,30,31）的响应消息发送到 启动块（23,25,26）。 响应消息包括使得能够独立地分别管理请求消息和响应消息的所述请求（21）和响应（22）网络的附加信息。

公开(公告)号：US20250103882A1

公开(公告)日：2025-03-27

申请号：US18583291

申请日：2024-02-21

Applicant: QUALCOMM Technologies, Inc.

Inventor： Dawid Jan KOPICZKO ,  Yuki Markus ASANO ,  Tijmen Pieter Frederik BLANKEVOORT

IPC: G06N3/08

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for efficiently adapting a machine learning model from a base task to a downstream task based on frozen matrices. An example method generally includes receiving an input for processing through a layer of a neural network. An output of the layer of the neural network is generated based on a first product, the first product being based on a first trainable scaling vector, a first frozen matrix, a second trainable scaling vector, a second frozen matrix, and the received input.

公开(公告)号：US20250103305A1

公开(公告)日：2025-03-27

申请号：US18538895

申请日：2023-12-13

Applicant: QUALCOMM Technologies, Inc.

Inventor： Natasha BUTT ,  Auke Joris WIGGERS ,  Corrado RAINONE ,  Blazej Jakub Manczak ,  Taco Sebastiaan Cohen

IPC: G06F8/35

Abstract: Systems and techniques are described for providing iterative policy-guided program synthesis. For example, a device may generate, based on a policy that receives input-output data of one or more tasks as input, a first set of programs, add the first set of programs and the input-output data to the training dataset to generate an updated training dataset, train the policy based on the first set of programs and the input-output data to generate an updated policy, identify, based on the updated policy, a second set of programs for second input-output data for a second set of tasks, add the second set of programs and second input-output data to the updated training dataset to generate a second updated training dataset; and train the updated policy based on the second set of programs and the second input-output data to generate a second updated policy.