公开(公告)号：US20210406056A1

公开(公告)日：2021-12-30

申请号：US16912788

申请日：2020-06-26

申请人： Intel Corporation

发明人： Vedvyas Shanbhogue ,  Doddaballapur Jayasimha ,  Raghu Ram Kondapalli

IPC分类号： G06F9/455 ,  G06F9/50 ,  G06F12/0873 ,  G06F12/1045

摘要： A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

公开(公告)号：US20210349833A1

公开(公告)日：2021-11-11

申请号：US16870363

申请日：2020-05-08

申请人： International Business Machines Corporation

发明人： Scott Alan Bauman ,  Daniel Frank Moertl ,  Robert Edward Galbraith

IPC分类号： G06F12/1045 ,  G06F12/02 ,  G06F9/50 ,  G06F16/17 ,  G06F16/16

摘要： A method and system of managing memory, the method including receiving a request for storage space in the memory system; obtaining a timestamp for a new Logical Unit Number (LUN); allocating a range of logical blocks to the new LUN in accordance with its requested size, the range of logical blocks including a starting logical block and a number of blocks; assigning the timestamp to the new LUN as the LUN creation timestamp; and saving the LUN creation timestamp with other metadata identifying the new LUN and the allocated logical blocks. Methods and system for deleting LUNs and using a deletion timestamp are disclosed as is a process to format a LUN.

公开(公告)号：US11157306B2

公开(公告)日：2021-10-26

申请号：US17006858

申请日：2020-08-30

申请人： Microsoft Technology Licensing, LLC

发明人： Yevgeniy Bak ,  Mehmet Iyigun ,  Arun U. Kishan

IPC分类号： G06F3/06 ,  G06F9/455 ,  G06F12/1045 ,  G06F12/109

摘要： To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

公开(公告)号：US20210311897A1

公开(公告)日：2021-10-07

申请号：US17026071

申请日：2020-09-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Krishna Teja MALLADI ,  Andrew CHANG ,  Ehsan M. NAJAFABADI

IPC分类号： G06F13/40 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/173 ,  G06F13/42 ,  G06F12/0808

摘要： A system and method for managing memory resources. In some embodiments the system includes a first server, including a stored-program processing circuit, a first network interface circuit, and a first memory module. The first memory module may include a first memory die, and a controller. The controller may be connected to the first memory die through a memory interface, to the stored-program processing circuit through a cache-coherent interface, and to the first network interface circuit.

公开(公告)号：US20210311856A1

公开(公告)日：2021-10-07

申请号：US17353675

申请日：2021-06-21

申请人： Sony Interactive Entertainment LLC

发明人： Mark Evan Cerny ,  David Simpson

IPC分类号： G06F11/36 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1045 ,  G06F9/30 ,  G06F9/46

摘要： A device having a Graphics Processing Unit (GPU) may be configured to selectively run in a normal mode or a timing testing mode. In the timing testing mode the device is configured to disrupt timing of processing that takes place on the GPU while running an application with the GPU and test the application for errors in device hardware component and/or software component synchronization while the device is running in the timing testing mode.

公开(公告)号：US20210303479A1

公开(公告)日：2021-09-30

申请号：US16834171

申请日：2020-03-30

申请人： Arm Limited

发明人： Peter Andrew RIOCREUX

IPC分类号： G06F12/1045 ,  G06F12/0831 ,  G06F12/084 ,  G06F9/46

摘要： Apparatus comprises address translation circuitry configured to access translation data defining a set of memory address translations; transaction handling circuitry to receive translation transactions and to receive invalidation transactions, each translation transaction defining one or more input memory addresses in an input memory address space to be translated to respective output memory addresses in an output memory address space, in which the transaction handling circuitry is configured to control the address translation circuitry to provide the output memory address as a translation response; in which each invalidation transaction defines at least a partial invalidation of the translation data; transaction tracking circuitry to associate an invalidation epoch, of a set of at least two invalidation epochs, with each translation transaction and with each invalidation transaction; and invalidation circuitry to store data defining a given invalidation transaction and, for translation transactions having the same invalidation epoch as the given invalidation transaction and handled by the address translation circuitry subsequent to the invalidation circuitry storing the data defining the given invalidation transaction, to process those translation transactions to indicate that a translation transaction is invalidated when the invalidation defined by the given invalidation transaction applies to that translation transaction; the invalidation circuitry being configured to forward at least an acknowledgement of the invalidation transaction for further processing by other apparatus in response to storage of the data by the invalidation circuitry.

公开(公告)号：US11093408B1

公开(公告)日：2021-08-17

申请号：US16429304

申请日：2019-06-03

申请人： Lightbits Labs Ltd.

发明人： Alexander Solganik ,  Adir Gabai ,  Shmuel Ben-Yehuda ,  Eran Kirzner ,  Abel Alkon Gordon

IPC分类号： G06F12/02 ,  G06F12/1045 ,  G06F12/0804

摘要： A system and a method of managing storage of cached data objects on a non-volatile memory (NVM) computer storage media including at least one NVM storage device, by at least one processor, may include: receiving one or more data objects having respective Time to Live (TTL) values; storing the one or more data objects and respective TTL values at one or more physical block addresses (PBAs) of the storage media; and performing a garbage collection (GC) process on one or more PBAs of the storage media based on at least one TTL value stored at a PBA of the storage media.

公开(公告)号：US20210248085A1

公开(公告)日：2021-08-12

申请号：US16973998

申请日：2018-09-28

申请人： Intel Corporation

发明人： Zhaojuan Bian ,  Kebing Wang

IPC分类号： G06F12/1045 ,  G06F12/06 ,  G06F12/0882 ,  G06F12/02 ,  G06F12/0871

摘要： Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.

公开(公告)号：US11080213B2

公开(公告)日：2021-08-03

申请号：US16700853

申请日：2019-12-02

申请人： INTEL CORPORATION

发明人： Balaji Vembu ,  Altug Koker ,  Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Niranjan L. Cooray

IPC分类号： G06F13/16 ,  G06T1/60 ,  G06F9/50 ,  G06F13/40 ,  G06F12/0802 ,  G06F12/1045 ,  G06F9/48 ,  G06F12/0875

摘要： An apparatus and method for dynamic provisioning and traffic control on a memory fabric. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated set of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment; and a plurality of queues associated with each VM at different levels of a memory interconnection fabric, the queues for a first VM to store memory traffic for that VM at the different levels of the memory interconnection fabric; arbitration hardware logic coupled to the plurality of queues and distributed across the different levels of the memory interconnection fabric, the arbitration hardware logic to cause memory traffic to be blocked from one or more upstream queues of the first VM upon detecting that a downstream queue associated with the first VM is full or at a specified threshold.

公开(公告)号：US11068410B2

公开(公告)日：2021-07-20

申请号：US16291154

申请日：2019-03-04

申请人： ETA SCALE AB

发明人： Alberto Ros ,  Stefanos Kaxiras

IPC分类号： G06F12/1045 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/0808

摘要： According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.