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公开(公告)号：US07078969B2
公开(公告)日：2006-07-18
申请号：US11209010
申请日：2005-08-22
IPC分类号： H03F3/45
CPC分类号： G06G7/30 , H03F3/45183
摘要： A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
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82.发明申请公开(公告)号：US20060104342A1
公开(公告)日：2006-05-18
申请号：US11284391
申请日：2005-11-21
申请人： Abhijit Shanbhag , Qian Yu , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud , Venugopal Balasubramonian
发明人： Abhijit Shanbhag , Qian Yu , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud , Venugopal Balasubramonian
IPC分类号： H03H7/30
CPC分类号： H04L25/03063 , H03H21/0012 , H03H2021/0096 , H04L25/0307 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
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83.发明授权Adaptive coefficient signal generator for adaptive signal equalizers with fractionally-spaced feedback 有权用于具有分数间隔反馈的自适应信号均衡器的自适应系数信号发生器公开(公告)号：US07039104B2
公开(公告)日：2006-05-02
申请号：US10322024
申请日：2002-12-17
申请人： Abhijit G. Shanbhag , Qian Yu , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud , Venugopal Balasubramonian
发明人： Abhijit G. Shanbhag , Qian Yu , Abhijit Phanse , Jishnu Bhattacharjee , Debanjan Mukherjee , Fabian Giroud , Venugopal Balasubramonian
CPC分类号： H04L25/03063 , H03H21/0012 , H03H2021/0096 , H04L25/0307 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.
摘要翻译： 一种用于具有分数间隔反馈的自适应信号均衡器中的自适应系数信号发生器。 代表反馈抽头系数的信号与定时内插参数一起产生，使得分数间隔的反馈电路动态地仿真符号间隔反馈电路。
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公开(公告)号：US07035330B2
公开(公告)日：2006-04-25
申请号：US10768408
申请日：2004-01-30
申请人： Abhijit G. Shanbhag , Qian Yu , Abhijit M. Phanse , Jishnu Bhatacharjee , Debanjan Mukherjee , Venugopal Balasubramonian , Fabian Giroud , Edem Ibragimov
发明人： Abhijit G. Shanbhag , Qian Yu , Abhijit M. Phanse , Jishnu Bhatacharjee , Debanjan Mukherjee , Venugopal Balasubramonian , Fabian Giroud , Edem Ibragimov
CPC分类号： H04L25/0307 , H03H21/0012 , H04L2025/0349 , H04L2025/03509 , H04L2025/03611
摘要： A decision feedback equalizer with dynamic feedback control for use in an adaptive signal equalizer. Timing within the decision feedback loop is dynamically controlled to optimize recovery of the data signal by the output signal slicer. The dynamic timing is controlled by a signal formed as a combination of feedback and feedforward signals. The feedback signal is an error signal related to a difference between pre-slicer and post-slicer signals. The feedforward signal is formed by differentiating and delaying the incoming data signal.
摘要翻译： 具有用于自适应信号均衡器的动态反馈控制的判决反馈均衡器。 动态控制决策反馈环路内的定时，以优化输出信号限幅器对数据信号的恢复。 动态定时由形成为反馈和前馈信号的组合的信号控制。 反馈信号是与预切片器和后切片器信号之间的差异相关的误差信号。 前馈信号通过差分和延迟输入数据信号来形成。
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公开(公告)号：US07031383B2
公开(公告)日：2006-04-18
申请号：US10117293
申请日：2002-04-05
CPC分类号： H04L25/03878
摘要： A compensation circuit for reducing intersymbol interference (ISI) products within an electrical data signal corresponding to a detected data signal received via a signal transmission medium provides for selective application of compensation to individual, discrete data signal components. According to one embodiment, one circuit branch processes the electrical data signal to substantially remove one distinct signal component representing an ISI product of some portion of the data symbol sequence. A second circuit branch approximately duplicates an ISI product of another portion of the data symbol sequence for removal by subtraction within a signal combiner from the compensated signal provided by the first circuit branch. A third circuit branch approximately duplicates an ISI product of still another portion of the data symbol sequence also for removal by subtraction within the signal combiner from the compensated signal provided by the first circuit branch.
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86.发明授权公开(公告)号：US07020402B2
公开(公告)日：2006-03-28
申请号：US10179689
申请日：2002-06-24
摘要： A crosstalk compensation engine for reducing signal crosstalk effects within a data signal. Demultiplexed data signals corresponding to multiplexed data signals received via a signal transmission medium are processed to significantly reduce one or more signal crosstalk products related to one or more interactions among the multiplexed data signals within the signal transmission medium. Such signal crosstalk products include those resulting from dense wavelength-division mutiplexing of the data signals used to provide the multiplexed data signals, four-wave mixing among the multiplexed data signals within the signal transmission medium, and cross-phase modulation among the multiplexed data signals within the signal transmission medium.
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87.发明授权公开(公告)号：US07016406B1
公开(公告)日：2006-03-21
申请号：US10426588
申请日：2003-04-29
申请人： Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Prashant Choudhary , Debanjan Mukherjee , Fabian Giroud , Edem Ibragimov
发明人： Abhijit Phanse , Abhijit G. Shanbhag , Qian Yu , Venugopal Balasubramonian , Jishnu Bhattacharjee , Prashant Choudhary , Debanjan Mukherjee , Fabian Giroud , Edem Ibragimov
IPC分类号： H03H7/40
CPC分类号： H04L25/03038 , H04L2025/03477 , H04L2025/03509 , H04L2025/03617
摘要： Tap coefficients for fractionally-spaced equalizers are updated iteratively using error statistics from an input bit stream and an output bit stream, such as from a forward error correction circuit. The process continues until the errors converge to a sufficiently small number. Knowledge of the error patterns are used apriori to adaptively change the tap coefficients in a feedforward filter.
摘要翻译： 使用来自输入比特流和输出比特流（例如来自前向纠错电路）的误差统计来迭代地更新用于分数间隔均衡器的抽头系数。 该过程继续，直到错误收敛到足够小的数量。 使用错误模式的知识用于自适应地改变前馈滤波器中的抽头系数。
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88.发明申请Differential amplifier having independently tunable base gain, peak gain and boost frequency, and uses of same 有权具有独立可调谐的基极增益，峰值增益和升压频率的差分放大器及其使用公开(公告)号：US20060028275A1
公开(公告)日：2006-02-09
申请号：US10911447
申请日：2004-08-03
IPC分类号： H03F3/45
CPC分类号： H03F3/193 , H03F1/42 , H03F3/45183 , H03F2200/111 , H03F2200/36 , H03F2200/451 , H03F2203/45638 , H03F2203/45641 , H03F2203/45686 , H03F2203/45712
摘要： A waveform shaping method comprises: (a) receiving link-distorted signal pulses; (b) passing the link-distorted signal pulses through a series of differential amplifiers each have independently tunable, base gains, peak boost gains, boost frequencies and boost bandwidths; and (c) adjusting one or more of the base gains, peak boost gains, boost frequencies and boost bandwidths of the series of differential amplifiers so as to realize a selective and progressive waveform re-shaping of the link-distorted signal pulses. In one embodiment, each amplifier in the series has first and second transistors with respective first and second drain nodes through which sum-constant currents respectively flow; and first and second, variable drain impedances (Zd1, Zd2) coupled to the first and second drain nodes, where each of the variable drain impedances has a non-negligible inductance (L), a non-negligible capacitance (C) and a non-negligible resistance (R), and where at least two of the R, L and C factors are programmably and independently adjustable so that an input voltage versus output voltage transfer function of the differential amplifier can exhibit a peak gain at a corresponding peak boost frequency which is greater than a base gain of the differential amplifier at 0 Hz.
摘要翻译： 波形整形方法包括：（a）接收链路失真的信号脉冲; （b）使链路失真的信号脉冲通过一系列差分放大器，每个差分放大器具有独立的可调谐，基极增益，峰值增益增益，升压频率和升压带宽; 和（c）调整一系列差分放大器的一个或多个基极增益，峰值升压增益，升压频率和升压带宽，以实现链路失真信号脉冲的选择性和逐行波形再整形。 在一个实施例中，该系列中的每个放大器具有第一和第二晶体管，其具有相应的第一和第二漏极节点，并且恒定电流通过该第一和第二漏极节流; 以及耦合到第一和第二漏极节点的第一和第二可变漏极阻抗（Zd 1，Zd 2），其中每个可变漏极阻抗具有不可忽略的电感（L），不可忽略的电容（C）和 不可忽略的电阻（R），并且其中R，L和C因子中的至少两个因素可编程和独立地可调节，使得差分放大器的输入电压对输出电压传递函数可以在相应峰值处显示峰值增益 升压频率大于差分放大器在0 Hz的基极增益。
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公开(公告)号：US06940352B2
公开(公告)日：2005-09-06
申请号：US10724561
申请日：2003-11-26
CPC分类号： G06G7/30 , H03F3/45183
摘要： A linear interpolator is provided that includes differential pairs of transistors biased such that a first input voltage may be multiplied by a factor r wherein 0≦r≦1 and such that a second input voltage may be multiplied by the complement factor (1−r). By combining the multiplied input voltages, a linear interpolation is provided based upon the factor r.
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公开(公告)号：US20050104705A1
公开(公告)日：2005-05-19
申请号：US10718449
申请日：2003-11-19
CPC分类号： H01F17/0013 , H01F2017/0046 , Y10T29/4902
摘要： An integrated circuit including a differentially excited symmetric microstrip inductor formed over multiple layers while maintaining both electrical and geometrical symmetry.
摘要翻译： 一种集成电路，其包括在多个层上形成的差分激励的对称微带电感器，同时保持电和几何对称性。
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