公开(公告)号：US20120104397A1

公开(公告)日：2012-05-03

申请号：US13244048

申请日：2011-09-23

Applicant: Jong-Hyun Choi ,  Na-Young Kim ,  Dae-Woo Lee

Inventor： Jong-Hyun Choi ,  Na-Young Kim ,  Dae-Woo Lee

IPC: H01L33/08 ,  H01L21/336

CPC classification number: H01L27/3262 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/14 ,  H01L27/3265 ,  H01L29/4908 ,  H01L51/56

Abstract: Provided are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes a thin-film transistor (TFT), which includes an active layer, a gate electrode, and source/drain electrodes; an organic electroluminescent device electrically connected to the TFT and includes a pixel electrode formed on the same layer as the gate electrode, an intermediate layer including an organic light emitting layer, and a counter electrode that are stacked in the order stated; and a capacitor, which includes a bottom electrode, which is formed on the same layer and of the same material as the active layer and is doped with an impurity; a top electrode formed on the same layer as the gate electrode; and a metal diffusion medium layer formed on the same layer as the source/drain electrodes and is connected to the bottom electrode.

Abstract translation: 提供一种有机发光显示装置及其制造方法。 有机发光显示装置包括薄膜晶体管（TFT），其包括有源层，栅极电极和源极/漏极电极; 电连接到TFT的有机电致发光器件，包括形成在与栅电极相同的层上的像素电极，包括有机发光层的中间层和按所述顺序层叠的对电极; 以及电容器，其包括形成在与所述有源层相同的层上并且与所述有源层相同的材料并且掺杂有杂质的底部电极; 形成在与栅极电极相同的层上的顶部电极; 以及形成在与源极/漏极电极相同的层上并与底部电极连接的金属扩散介质层。

公开(公告)号：US20110068337A1

公开(公告)日：2011-03-24

申请号：US12923434

申请日：2010-09-21

Applicant: Jong-Hyun Choi ,  Ji-Yong Noh ,  Jang-Soon Im ,  Dae-Woo Lee

Inventor： Jong-Hyun Choi ,  Ji-Yong Noh ,  Jang-Soon Im ,  Dae-Woo Lee

IPC: H01L29/12 ,  H01L33/08

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/78606

Abstract: A display includes a substrate main body, a thin film transistor (TFT) on the substrate main body, the TFT including an oxide semiconductor layer and a metal oxide film sequentially stacked on top of each other.

Abstract translation: 显示器包括基板主体，在基板主体上的薄膜晶体管（TFT），TFT包括依次层叠在一起的氧化物半导体层和金属氧化物膜。

公开(公告)号：US20080291198A1

公开(公告)日：2008-11-27

申请号：US12100707

申请日：2008-04-10

Applicant: Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

Inventor： Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.

Abstract translation: 提供了一种使用具有多个处理元件（PE）的并行处理器执行三维（3D）图形几何变换的方法。 该方法包括使用并行处理器对第一组顶点向量执行模型/视图变换和投影变换; 使用通用处理器计算用于第一组顶点矢量的四元数校正的值，并且同时对第二组顶点矢量执行模型/视图变换和投影变换; 对所述第一组顶点向量进行四元数校正和画面映射，并且使用所述通用处理器同时计算用于所述第二组顶点向量的四元数校正的值; 并对第二组顶点向量执行四元数校正和屏幕映射。

公开(公告)号：US20080273520A1

公开(公告)日：2008-11-06

申请号：US12113075

申请日：2008-04-30

Applicant: Ki-Back KIM ,  Dong-Soo PARK ,  Dae-Woo LEE ,  Ji-Cheol LEE ,  Jung-Shin PARK ,  Seong-Min KIM

Inventor： Ki-Back KIM ,  Dong-Soo PARK ,  Dae-Woo LEE ,  Ji-Cheol LEE ,  Jung-Shin PARK ,  Seong-Min KIM

IPC: H04J3/00

CPC classification number: H04L47/824 ,  H04L47/70 ,  H04L47/78 ,  H04M15/66 ,  H04W4/00 ,  H04W28/18 ,  H04W28/24

Abstract: A communication network architecture including a broadband radio access network is provided. The architecture includes a terminal for transmitting an application layer service request message to request a service, a Policy Charging Rule Function (PCRF) for generating Quality of Service (QoS) parameters of an Internet Protocol (IP) layer using QoS parameters of an application layer contained in the application layer service request message, a first Policy Decision Function (PDF) for generating one or more QoS parameters of the IP layer in addition to the IP layer QoS parameters generated at the PCRF and a second PDF for generating a QoS parameter set of a radio access network using the IP layer QoS parameters generated at the PCRF and the one or more IP layer QoS parameters generated at the first PDF. The communication network guarantees an end-to-end QoS.

Abstract translation: 提供了包括宽带无线电接入网络的通信网络架构。 该架构包括用于发送应用层服务请求消息以请求服务的终端，用于使用应用层的QoS参数来生成因特网协议（IP）层的服务质量（QoS）参数的策略计费规则功能（PCRF） 包含在所述应用层服务请求消息中的第一策略决策功能（PDF），用于生成所述IPF层生成的IP层QoS参数的IP层的一个或多个QoS参数的第一策略决策功能（PDF）和用于生成QoS参数集的第二PDF 使用在PCRF处生成的IP层QoS参数和在第一PDF生成的一个或多个IP层QoS参数的无线电接入网络。 通信网络保证端到端的QoS。

公开(公告)号：US20080133879A1

公开(公告)日：2008-06-05

申请号：US11906381

申请日：2007-10-01

Applicant: Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

Inventor： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/30189

Abstract: Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.

Abstract translation: 提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。 每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。 由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

公开(公告)号：US20080129359A1

公开(公告)日：2008-06-05

申请号：US11945387

申请日：2007-11-27

Applicant: Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

Inventor： Dae Woo LEE ,  Yil Suk YANG ,  Ik Jae CHUN ,  Chun Gi LYUH ,  Tae Moon ROH ,  Jong Dae KIM

IPC: H03K3/356

CPC classification number: H03K3/0375

Abstract: Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

Abstract translation: 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

公开(公告)号：US20070126486A1

公开(公告)日：2007-06-07

申请号：US11607743

申请日：2006-12-01

Applicant: Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

Inventor： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

IPC: H03K3/00

CPC classification number: H03K3/356156 ,  H03K3/012

Abstract: Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

Abstract translation: 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

公开(公告)号：US06887772B2

公开(公告)日：2005-05-03

申请号：US10721970

申请日：2003-11-24

Applicant: Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

Inventor： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

IPC: H05B33/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8238

CPC classification number: H01L21/823462 ,  H01L27/088 ,  H01L27/1203

Abstract: The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

Abstract translation: 本发明涉及形成在SOI衬底上的高电压器件和低电压器件的结构及其制造方法，其特征在于SOI衬底中硅器件区域的低电压器件区域较高 比高压器件区域逐步，并且形成高压器件的硅器件​​区域的厚度等于低压器件中的源极和漏极的杂质的结深度。 因此，SOI衬底中的硅器件区域被分成高压区域和低电压区域，并且通过氧化生长方法在其间形成步骤，使得可以制造具有低结电容的高电压器件，并且低电压 与传统CMOS工艺兼容的器件和器件特性也可以同时进行。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

Applicant: Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

Inventor： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC: H03L500

CPC classification number: H03K19/0016

Abstract: The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

Abstract translation: 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。

公开(公告)号：US06617656B2

公开(公告)日：2003-09-09

申请号：US10179492

申请日：2002-06-24

Applicant: Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

Inventor： Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Yil Suk Yang ,  Jong Dae Kim

IPC: H01L2978

CPC classification number: H01L29/0634 ,  H01L29/7835

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract translation: 本发明提供一种具有晶格型漂移区域的EDMOS（延伸漏极MOS）器件及其制造方法。 在n沟道EDMOS（nEDMOS）的情况下，漂移区域具有晶格结构，其中具有高浓度的n晶格和具有低浓度的p晶格交替排列。 当施加漏极电压时，耗尽层被n晶格和p晶格的pn结突然延伸，使得整个漂移区域容易耗尽。 因此，器件的击穿电压增加，并且由于具有高浓度的n晶格，器件的导通电阻降低。