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13 条记录 (耗时 0.024 秒)

    Multi-threshold CMOS latch circuit
    1.
    发明申请
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US20070126486A1

    公开(公告)日：2007-06-07

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/00

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

    Multi-threshold CMOS latch circuit
    2.
    发明授权
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US07391249B2

    公开(公告)日：2008-06-24

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

    Pixel driving circuit with threshold voltage compensation circuit
    3.
    发明申请
    Pixel driving circuit with threshold voltage compensation circuit 审中-公开
    带阈值电压补偿电路的像素驱动电路

    公开(公告)号：US20070126663A1

    公开(公告)日：2007-06-07

    申请号：US11521338

    申请日：2006-09-14

    申请人： Gyu Hyun Kim ,  Yil Suk Yang ,  Dae Woo Lee ,  Jong Dae Kim

    发明人： Gyu Hyun Kim ,  Yil Suk Yang ,  Dae Woo Lee ,  Jong Dae Kim

    IPC分类号： G09G3/30

    CPC分类号： G09G3/3241 ,  G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0842

    摘要： Provided is a pixel driving circuit including a threshold voltage compensation circuit. The pixel driving circuit includes a diode-connected type first transistor through which input current data flows; a second transistor copying the current data flowing through the first transistor; a third transistor connected in series to the second transistor; a fourth transistor diode-connected between a power supply voltage terminal and the third transistor; and a driving transistor connected to the power supply voltage terminal, copying the current data flowing through the third transistor, and providing the data to a light emitting diode. Since the pixel driving circuit compensates for variation in the threshold voltage of the driving transistor driving each pixel, brightness uniformity of pixels according to applied current data can be maintained.

    摘要翻译： 提供了包括阈值电压补偿电路的像素驱动电路。 像素驱动电路包括输入电流数据流过的二极管连接型第一晶体管; 第二晶体管复制流过第一晶体管的电流数据; 与第二晶体管串联连接的第三晶体管; 连接在电源电压端子和第三晶体管之间的第四晶体管二极管; 以及连接到电源电压端子的驱动晶体管，复制流过第三晶体管的电流数据，并将数据提供给发光二极管。 由于像素驱动电路补偿驱动每个像素的驱动晶体管的阈值电压的变化，所以可以保持根据所施加的当前数据的像素的亮度均匀性。

    Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor
    4.
    发明申请
    Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor 有权
    多位Σ-Δ调制器和具有一个数模转换器的数/模转换器

    公开(公告)号：US20070126615A1

    公开(公告)日：2007-06-07

    申请号：US11588455

    申请日：2006-10-27

    申请人： Yi Gyeong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Min Hyung Cho ,  Seung Chul Lee ,  Gyu Hyun Kim

    发明人： Yi Gyeong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Min Hyung Cho ,  Seung Chul Lee ,  Gyu Hyun Kim

    IPC分类号： H03M1/66

    CPC分类号： H03M3/352 ,  H03M3/424 ,  H03M3/464

    摘要： A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.

    摘要翻译： 提供了一种用于Σ-Δ调制器的数模转换器（DAC）。 DAC具有使用运算放大器（OP放大器）的开关电容器结构，并且使用仅采用单端形式的一个电容器的开关方法来执行超过3电平的功能。 因此，不会发生由电容器失配引起的DAC非线性，并且DAC的输出电平的数量增加。 此外，DAC电容器可以被施加到通用DAC以增加DAC输出电平与电容器的比率。

    Method for forming semiconductor memory capacitor without cell-to-cell bridges
    7.
    发明授权
    Method for forming semiconductor memory capacitor without cell-to-cell bridges 失效
    用于形成半导体存储器电容器而不使用电池到电池桥的方法

    公开(公告)号：US07498267B2

    公开(公告)日：2009-03-03

    申请号：US11776750

    申请日：2007-07-12

    申请人： Gyu Hyun Kim ,  Yong Soo Choi

    发明人： Gyu Hyun Kim ,  Yong Soo Choi

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L28/91 ,  H01L27/10852 ,  Y10S438/905

    摘要： A capacitor is formed by forming a mold insulating layer with a plurality of storage node holes over a semiconductor substrate. A metal storage node is formed on the surface of each of the storage node holes in the mold insulating layer. The mold insulating layer is removed by performing the following steps: loading the semiconductor substrate with the storage node in the chamber for in-situ cleaning, rinsing, and drying processes; removing the mold insulating layer by an etchant in the chamber; then rinsing the semiconductor substrate by introducing deionized water into the chamber while discharging the etchant out of the chamber; finally rinsing the rinsed semiconductor substrate with a mixed solution of the deionized water and organic solvent; drying the finally rinsed semiconductor substrate by IPA vapor in the chamber while discharging the mixed solution of the deionized water and organic solvent out of the chamber.

    摘要翻译： 通过在半导体衬底上形成具有多个存储节点孔的模具绝缘层来形成电容器。 金属存储节点形成在模具绝缘层中的每个存储节点孔的表面上。 通过执行以下步骤去除模具绝缘层：将具有存储节点的半导体衬底装载在用于原位清洁，漂洗和干燥过程的室中; 通过腔室中的蚀刻剂去除模具绝缘层; 然后通过将去离子水引入室中来冲洗半导体衬底，同时将蚀刻剂排出室; 最后用去离子水和有机溶剂的混合溶液冲洗冲洗的半导体衬底; 在室内通过IPA蒸气干燥最终漂洗的半导体衬底，同时将去离子水和有机溶剂的混合溶液排出室外。

    Method for forming capacitor of semiconductor device
    9.
    发明授权
    Method for forming capacitor of semiconductor device 有权
    形成半导体器件电容器的方法

    公开(公告)号：US07112506B2

    公开(公告)日：2006-09-26

    申请号：US10878747

    申请日：2004-06-28

    申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

    发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

    IPC分类号： H01L21/20

    CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/75

    摘要： Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

    摘要翻译： 公开了一种形成半导体器件的电容器的方法。 蚀刻停止层，第一氧化物层和第二氧化物层依次沉积在基板的绝缘中间层上。 形成了绝缘中间层的插塞之上的蚀刻停止层的部分露出的接触孔。 接触孔由具有比第二氧化物层高的第一氧化物层的蚀刻选择性的清洗溶液清洁，从而扩大接触孔的下部。 在接触孔和第二氧化物层的表面上形成间隔氮化物层。 去除位于第二氧化物层上和插塞上方的间隔氮化物层的一部分以及位于插塞上的蚀刻停止层的部分。 在间隔氮化物层段上形成双重多晶硅层。

    Method for manufacturing semiconductor device
    10.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06893914B2

    公开(公告)日：2005-05-17

    申请号：US10603895

    申请日：2003-06-25

    申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

    发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

    IPC分类号： H01L21/308 ,  H01L21/304 ,  H01L21/306 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10894 ,  H01L21/31133 ,  H01L21/3165 ,  H01L27/10814

    摘要： A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.

    摘要翻译： 这里描述了一种用于制造半导体器件的方法，其中通过在电池区域中的氧化膜的湿蚀刻工艺中选择性地蚀刻在电池区中用于防止电池之间的桥接的氧化膜形成圆柱形电容器。 通过用光致抗蚀剂膜覆盖外围电路区域并选择性地蚀刻电池区域中的氧化膜，使形成在电池区域中的层间绝缘膜与形成在外围电路区域中的层间绝缘膜之间的阶梯差被最小化，以形成圆柱形 电容器，从而简化制造过程。 此外，通过使用单个湿站进行简单的湿式蚀刻处理来防止电池之间的桥接，而不进行用于去除氧化膜和光致抗蚀剂膜图案的单独的干蚀刻工艺，从而提高器件的产量。