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    Organic light emitting diode display apparatus and method of manufacturing the same
    7.
    发明授权
    Organic light emitting diode display apparatus and method of manufacturing the same 有权
    有机发光二极管显示装置及其制造方法

    公开(公告)号：US08164252B2

    公开(公告)日：2012-04-24

    申请号：US12458371

    申请日：2009-07-09

    Applicant: Dae-Woo Lee ,  Do-Hyun Kwon ,  Dae-Woo Kim

    Inventor： Dae-Woo Lee ,  Do-Hyun Kwon ,  Dae-Woo Kim

    IPC: H01J1/64

    CPC classification number: H01L27/3246 ,  C08G2261/1424 ,  C08G2261/3142 ,  C08G2261/3221 ,  C08G2261/3223 ,  C08G2261/3422 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0039 ,  H01L51/0078

    Abstract: An organic light emitting diode (OLED) display apparatus, including a substrate, at least one thin film transistor (TFT) on the substrate, an insulating layer covering the at least one TFT and having a via hole and a groove, a first electrode on the insulating layer and electrically connected to the at least one TFT through the via hole, a pixel define layer on the first electrode and the groove, the pixel define layer having an opening that exposes the first electrode; an intermediate layer electrically connected to the first electrode through the opening, the intermediate layer including an organic emissive layer, and a second electrode on the intermediate layer. The organic emissive layer may be easily formed in the opening because a step between the organic emissive layer and the pixel define layer may be reduced as a portion of pixel define layer fills the groove.

    Abstract translation: 一种有机发光二极管（OLED）显示装置，包括基板，在基板上的至少一个薄膜晶体管（TFT），覆盖至少一个TFT的绝缘层，并具有通孔和沟槽;第一电极， 所述绝缘层通过所述通孔与所述至少一个TFT电连接，所述第一电极和所述沟槽上的像素限定层，所述像素限定层具有暴露所述第一电极的开口; 通过所述开口电连接到所述第一电极的中间层，所述中间层包括有机发光层，以及在所述中间层上的第二电极。 有机发光层可以容易地形成在开口中，因为有机发光层和像素限定层之间的步骤可以随着像素限定层的一部分填充凹槽而减小。

    Low-power clock gating circuit
    10.
    发明授权
    Low-power clock gating circuit 有权
    低功耗时钟门控电路

    公开(公告)号：US07576582B2

    公开(公告)日：2009-08-18

    申请号：US11945387

    申请日：2007-11-27

    Applicant: Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

    Inventor： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

    IPC: H03K3/289

    CPC classification number: H03K3/0375

    Abstract: Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

    Abstract translation: 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

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