公开(公告)号：US20080291198A1

公开(公告)日：2008-11-27

申请号：US12100707

申请日：2008-04-10

申请人： Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

发明人： Ik Jae Chun ,  Jung Hee Suk ,  Yil Suk Yang ,  Dae Woo Lee ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Woo Lee

IPC分类号： G06T15/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.

摘要翻译： 提供了一种使用具有多个处理元件（PE）的并行处理器执行三维（3D）图形几何变换的方法。 该方法包括使用并行处理器对第一组顶点向量执行模型/视图变换和投影变换; 使用通用处理器计算用于第一组顶点矢量的四元数校正的值，并且同时对第二组顶点矢量执行模型/视图变换和投影变换; 对所述第一组顶点向量进行四元数校正和画面映射，并且使用所述通用处理器同时计算用于所述第二组顶点向量的四元数校正的值; 并对第二组顶点向量执行四元数校正和屏幕映射。

公开(公告)号：US08731059B2

公开(公告)日：2014-05-20

申请号：US12105745

申请日：2008-04-18

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Ik Jae Chun ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Jung Hoon Kim

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N7/26 ,  H04N7/50 ,  H04N7/36

CPC分类号： H04N19/00521 ,  H04N19/102 ,  H04N19/122 ,  H04N19/134 ,  H04N19/436 ,  H04N19/57 ,  H04N19/61 ,  H04N19/86

摘要： An apparatus that calculates a Sum of Absolute Differences (SAD) for motion estimation of a variable block capable of parallelly calculating SAD values with respect to multiple current frame macroblocks at a time is presented. The apparatus includes a PE array unit including at least one Processing Element (PE) that is aligned in the form of a matrix, and parallelly calculating a SAD value of at least one pixel provided in multiple serial current frame macroblocks, a local memory including current frame macroblock data, reference frame macroblock data, and reference frame search area data, and transmitting the data to each PE that is provided in the PE array unit, and a controller for making a command for the data that are provided in the local memory to be transmitted corresponding to at least one pixel, on which each PE provided in the PE array unit performs calculation.

摘要翻译： 提出了一种计算能够相对于多个当前帧宏块同时计算SAD值的可变块的运动估计的绝对差（SAD）的装置。 该装置包括PE阵列单元，该PE阵列单元包括以矩阵的形式排列的至少一个处理元件（PE），并且并行地计算在多个串行当前帧宏块中提供的至少一个像素的SAD值，包括电流 帧宏块数据，参考帧宏块数据和参考帧搜索区域数据，并且将数据发送到在PE阵列单元中提供的每个PE，以及用于对提供在本地存储器中的数据进行命令的控制器 对应于至少一个像素，其中PE阵列单元中提供的每个PE执行计算。

公开(公告)号：US07576582B2

公开(公告)日：2009-08-18

申请号：US11945387

申请日：2007-11-27

申请人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H03K3/289

CPC分类号： H03K3/0375

摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

公开(公告)号：US08150903B2

公开(公告)日：2012-04-03

申请号：US12136107

申请日：2008-06-10

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F7/57

CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

公开(公告)号：US07769981B2

公开(公告)日：2010-08-03

申请号：US12045844

申请日：2008-03-11

申请人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

发明人： Chun Gi Lyuh ,  Yil Suk Yang ,  Se Wan Heo ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim ,  Ki Chul Kim ,  Se Hoon Yoo

IPC分类号： G06F15/80

CPC分类号： G06F15/8007

摘要： Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.

摘要翻译： 提供了一种用于支持浮点运算的并行处理器。 并行处理器具有灵活的结构，便于开发涉及多媒体计算的并行算法，需要较低的硬件成本，并且消耗低功耗。 为了支持浮点运算，并行处理器使用浮点累加器和浮点乘法的标志。 使用并行处理器，可以以低成本在三维（3D）图形处理中处理几何变换操作。 此外，可以通过分区单指令多数据（SIMD）方法和有条件执行指令的方法来最小化用于指令的总线宽度的成本。

公开(公告)号：US07403178B2

公开(公告)日：2008-07-22

申请号：US10817838

申请日：2004-04-06

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Dae Woo Lee ,  Tae Moon Roh ,  Il Yong Park ,  Sung Ku Kwon ,  Byoung Gon Yu

IPC分类号： G09G3/30 ,  G09G3/20 ,  G09G3/22

CPC分类号： G09G3/30 ,  G09G2310/027 ,  G09G2320/0276

摘要： Provided is a source driver circuit for an active matrix electroluminescent (EL) display including a digital-to-analog converter/ramp circuit for converting a digital signal into an analog signal, and generating a ramp signal in this process, simultaneously, whereby high degree of integration would be possible since a conventional complicated circuit is not required and gray scale with the high characteristic can be implanted, regardless of a change of a temperature or a threshold voltage.

摘要翻译： 提供了一种用于有源矩阵电致发光（EL）显示器的源极驱动电路，其包括用于将数字信号转换为模拟信号的数模转换器/斜坡电路，并且在该过程中同时产生斜坡信号，由此高度 的集成是可能的，因为不需要常规的复杂电路，而不管温度或阈值电压的变化，都可以植入具有高特性的灰度级。

公开(公告)号：US06855581B2

公开(公告)日：2005-02-15

申请号：US10153975

申请日：2002-05-23

申请人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

发明人： Tae Moon Roh ,  Dae Woo Lee ,  Yil Suk Yang ,  Il Yong Park ,  Sang Gi Kim ,  Jin Gun Koo ,  Jong Dae Kim

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.

摘要翻译： 本发明涉及使用其中绝缘膜和硅层依次层叠在硅衬底上的SOI结构的衬底的高压大功率集成电路器件的制造方法。 该方法包括以下步骤：在硅层上依次形成氧化物膜和光致抗蚀剂膜，然后使用沟槽掩模进行光刻工艺以对光刻胶膜进行图案化; 使用图案化的光致抗蚀剂膜作为掩模来图案化氧化膜，然后在图案化之后除去光致抗蚀剂膜; 使用所述图案化氧化膜作为掩模蚀刻所述硅层，直到所述绝缘膜暴露以形成沟槽; 在包括沟槽的整个表面上形成氮化物膜，执行退火处理并在整个表面上沉积多晶硅，使得沟槽被埋置; 并且顺序地去除多晶硅和氮化物膜，直到硅层暴露以使表面变平，从而形成用于在沟槽内的器件之间进行电隔离的器件隔离膜。 因此，本发明能够有效地降低高压大功率器件与逻辑CMOS器件之间的沟槽的隔离面积，能够容易地控制深井的浓度。

公开(公告)号：US20080133879A1

公开(公告)日：2008-06-05

申请号：US11906381

申请日：2007-10-01

申请人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

发明人： Yil Suk Yang ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim ,  Chun Gi Lyuh

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30181 ,  G06F9/30189

摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.

摘要翻译： 提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。 每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。 由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

公开(公告)号：US06887772B2

公开(公告)日：2005-05-03

申请号：US10721970

申请日：2003-11-24

申请人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Tae Moon Roh ,  Yil Suk Yang ,  Il Yong Park ,  Byoung Gon Yu ,  Jong Dae Kim

IPC分类号： H05B33/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8238

CPC分类号： H01L21/823462 ,  H01L27/088 ,  H01L27/1203

摘要： The present invention relates to structures of a high voltage device and a low voltage device formed on a SOI substrate and a method for manufacturing the same, and it is characterized in which the low voltage device region of silicon device regions in a SOI substrate is higher than the high voltage device region by steps, and a thickness of the silicon device region, where the high voltage device is formed, is equal to a junction depth of impurities of a source and drain in the low voltage device. Accordingly, silicon device regions in the SOI substrate are divided into the high voltage region and the low voltage region and steps are formed there between by oxidation growth method, so that the high voltage device having low junction capacitance can be made, and the low voltage device compatible with the conventional CMOS process and device characteristics can also be made at the same time.

摘要翻译： 本发明涉及形成在SOI衬底上的高电压器件和低电压器件的结构及其制造方法，其特征在于SOI衬底中硅器件区域的低电压器件区域较高 比高压器件区域逐步，并且形成高压器件的硅器件​​区域的厚度等于低压器件中的源极和漏极的杂质的结深度。 因此，SOI衬底中的硅器件区域被分成高压区域和低电压区域，并且通过氧化生长方法在其间形成步骤，使得可以制造具有低结电容的高电压器件，并且低电压 与传统CMOS工艺兼容的器件和器件特性也可以同时进行。

公开(公告)号：US06774697B2

公开(公告)日：2004-08-10

申请号：US10325929

申请日：2002-12-23

申请人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

发明人： Yil Suk Yang ,  Jong Dae Kim ,  Tae Moon Roh ,  Jin Gun Koo ,  Dae Woo Lee ,  Sang Gi Kim ,  Il Yong Park

IPC分类号： H03L500

CPC分类号： H03K19/0016

摘要： The present invention relates to an input and output port circuit. The input and output port circuit comprises a signal register for storing output signals, an input/output register at which an input/output control signal for determining an input/output direction is stored, a plurality of control registers, a power supply switch circuit for selectively supplying a low voltage or a high voltage depending on a power mode control signal, a signal direction control circuit for determining the direction of the signal depending on a value of the signal register and a value of the input/output register, an output control circuit driven depending on the value of the control register and an output of the signal direction control circuit, and an output driving circuit for outputting the low voltage, the high voltage or the ground value depending on an output of the signal direction control circuit and an output of the output control circuit. The high voltage and the low voltage can be simultaneously driven using only a single output driving circuit and the single output driving circuit is constructed in multiple stages and is selectively driven by the output control register. Therefore, the power consumption can be saved.

摘要翻译： 本发明涉及输入和输出端口电路。 输入输出端口电路包括用于存储输出信号的信号寄存器，存储用于确定输入/输出方向的输入/输出控制信号的输入/输出寄存器，多个控制寄存器，用于 选择性地根据功率模式控制信号提供低电压或高电压;信号方向控制电路，用于根据信号寄存器的值确定信号的方向，以及输入/输出寄存器的值，输出控制 电路根据控制寄存器的值和信号方向控制电路的输出驱动，以及输出驱动电路，用于根据信号方向控制电路的输出输出低电压，高电压或接地值，以及 输出控制电路的输出。 高电压和低电压可以使用单个输出驱动电路同时驱动，单输出驱动电路构成多级，由输出控制寄存器有选择地驱动。 因此，可以节省功耗。