公开(公告)号：US07466687B2

公开(公告)日：2008-12-16

申请号：US10425097

申请日：2003-04-28

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Gordon Taylor Davis ,  Clark Debs Jeffries

IPC: H04L12/28

CPC classification number: H04L45/00 ,  H04L12/4625 ,  H04L45/54 ,  H04L45/7453 ,  H04L63/0263

Abstract: A method and system for encoding a set of range labels for each parameter field in a packet classification key in such a way as to require preferably only a single entry per rule in a final processing stage of a packet classifier. Multiple rules are sorted accorded to their respective significance. A range, based on a parameter in the packet header, is previously determined. Multiple rules are evaluated according to an overlapping of rules according to different ranges. Upon a determination that two or more rules overlap, each overlapping rule is expanded into multiple unique segments that identify unique range intersections. Each cluster of overlapping ranges is then offset so that at least one bit in a range for the rule remains unchanged. The range segments are then converted from binary to Gray code, which results in the ability to determine a CAM entry to use for each range.

Abstract translation: 一种方法和系统，用于以分组分类密钥中的每个参数字段的一组范围标签进行编码，以便在分组分类器的最后处理阶段中优选地仅需要每个规则仅一个条目。 根据各自的意义对多个规则进行排序。 预先确定基于分组报头中的参数的范围。 根据不同范围的规则重叠来评估多个规则。 在确定两个或更多个规则重叠时，每个重叠规则被扩展为识别唯一范围交点的多个唯一段。 然后，每个重叠范围的簇被偏移，使得该规则的范围中的至少一个位保持不变。 范围段然后从二进制转换为格雷码，这导致确定每个范围使用的CAM条目的能力。

公开(公告)号：US20080222324A1

公开(公告)日：2008-09-11

申请号：US12120419

申请日：2008-05-14

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC: G06F5/00

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract translation: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07293158B2

公开(公告)日：2007-11-06

申请号：US11070060

申请日：2005-03-02

Applicant: Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

Inventor： Jean Louis Calvignac ,  Chih-jen Chang ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC: G06F15/00 ,  G06F12/00

CPC classification number: H04L49/901 ,  H04L49/90

Abstract: Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.

Abstract translation: 公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。 实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。 网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。 实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。 每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。 在R-M-W周期的写周期期间，递增的值被写入存储器。 写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

公开(公告)号：US07167471B2

公开(公告)日：2007-01-23

申请号：US09940758

申请日：2001-08-28

Applicant: Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

Inventor： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Michael Steven Siegel

IPC: H04L12/56

CPC classification number: H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

Abstract: A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

Abstract translation: 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

公开(公告)号：US07161961B2

公开(公告)日：2007-01-09

申请号：US09880450

申请日：2001-06-13

Applicant: Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

Inventor： Kenneth James Barker ,  Rolf Clauberg ,  Jean Louis Calvignac ,  Andreas Guenther Herkersdorf ,  Fabrice Jean Verplanken ,  David John Webb

IPC: H04J3/00 ,  H04J3/02 ,  H04L12/56

CPC classification number: H04J3/1611 ,  H04J3/0685 ,  H04J3/22 ,  H04J2203/0089

Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

Abstract translation: 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 此外，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中，不存在SDH，对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

公开(公告)号：US07149212B2

公开(公告)日：2006-12-12

申请号：US10095844

申请日：2002-03-12

Applicant: Jean Louis Calvignac ,  Marco Heddes ,  Joseph Franklin Logan

Inventor： Jean Louis Calvignac ,  Marco Heddes ,  Joseph Franklin Logan

IPC: H04L12/50

CPC classification number: H04L49/9063 ,  H04L29/06 ,  H04L49/90 ,  H04L49/901 ,  H04L69/12 ,  H04L69/22

Abstract: An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.

公开(公告)号：US07139753B2

公开(公告)日：2006-11-21

申请号：US10650327

申请日：2003-08-28

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F7/00 ,  H04L12/28

CPC classification number: H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

Abstract: Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

Abstract translation: 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

公开(公告)号：US07133942B2

公开(公告)日：2006-11-07

申请号：US10017171

申请日：2001-12-07

Applicant: Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

Inventor： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

IPC: G06F13/00 ,  G06F13/14 ,  G08C15/00 ,  H04J3/22

CPC classification number: G06F15/8053

Abstract: A parallel processing system includes a plurality of stages operatively coupled in parallel and operating simultaneously. Each stage including a process unit generating a predetermined function and a buffer coupled via a slow output and a slow input ports to the process unit. The buffer also includes a fast input port and a fast output port. A controller drives the buffer to operate in a Slow Read Phase when data is written from the buffer into the process unit, a Slow Write Phase when data is written into the buffer from the process unit, a Fast Write Phase when data is written at a fast rate into the buffer and a Fast Read Phase when data is read from the buffer.

公开(公告)号：US07106730B1

公开(公告)日：2006-09-12

申请号：US09546833

申请日：2000-04-11

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: H04L12/56

CPC classification number: H04L49/30

Abstract: A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.

Abstract translation: 一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。 接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。 帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。 通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。 出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。 通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

公开(公告)号：US07085850B2

公开(公告)日：2006-08-01

申请号：US09934886

申请日：2001-08-22

Applicant: Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

Inventor： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

IPC: G06F15/16

CPC classification number: H04L29/06 ,  H04L69/22

Abstract: A stateless message-passing scheme for interactions between a network processor and a coprocessor is provided. The network processor, when receiving data frames for transmission from a network element to another network element encapsulates the entire packet that it receives within a frame. In this frame, there is provided a header field and a data field. The data field contains the data that needs to be transferred, and the header field contains all of the information regarding the deep-processing that the coprocessor is to perform so that no information of any type need be stored either by the network processor or separately regarding the processing of the data in the data packet. The coprocessor performs the operation designated by the header and returns the altered packet and header to the network processor.