公开(公告)号：US20100198894A1

公开(公告)日：2010-08-05

申请号：US12362879

申请日：2009-01-30

Applicant: Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

Inventor： Kameran Azadet ,  Jian-Guo Chen ,  Samer Hijazi ,  Joseph Williams

IPC: G06F7/52 ,  G06F7/00 ,  G06F7/38

CPC classification number: G06F7/556 ,  G06F1/035 ,  G06F2101/10

Abstract: A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q1, larger than a specified value, x0, and a second fractional part, q2, smaller than the specified value, x0; computing 2q2 using a polynomial approximation, such as a cubic approximation; obtaining 2q1 from a look-up table; and evaluating the exponential function for the input value, x, by multiplying 2q2, 2q1 and 2N together. Look-up table entries have a fewer number of bits than a number of bits in the input value, x.

Abstract translation: 提供了一种数字信号处理器，其具有使用缩减的查找表的具有指数函数的指令集。 所公开的数字信号处理器通过将输入值x分解为整数部分N来估算输入值x的指数函数，N，大于指定值x0的第一小数部分q1，以及第二分数 部分，q2，小于指定值x0; 使用多项式近似计算2q2，例如立方近似; 从查表中获得2q1; 并且通过将2q2,2q1和2N相乘来估计输入值x的指数函数。 查找表条目具有比输入值x中的位数少的位数。

公开(公告)号：US07502418B2

公开(公告)日：2009-03-10

申请号：US10022659

申请日：2001-12-18

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04L5/12

CPC classification number: H04L25/4923 ,  H04L25/03229 ,  H04L2025/03363

Abstract: A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm.

Abstract translation: 公开了一种用于联合均衡和解码多级代码的方法和装置，例如在色散信道上传输的MLT-3码。 MLT-3代码被视为由有限状态机使用在各种状态之间具有状态依赖性的网格生成的代码。 超级网格将MLT-3网格与网络格式的通道连接起来。 接收信号的联合均衡和解码可以使用超级格子进行。 公开了一种序列检测器，其使用超级格或相应的缩减状态网格对所接收的信号执行联合均衡和解码，以解码MLT-3编码数据位。 可以使用应用最优维特比算法或缩减复杂度序列估计方法（例如缩减状态序列估计（RSSE）算法）的最大似然序列估计来体现序列检测器。

公开(公告)号：US20080317179A1

公开(公告)日：2008-12-25

申请号：US12039474

申请日：2008-02-28

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04B1/10

CPC classification number: H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed, with an increased throughput using precomputation (look-ahead), with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract translation: 公开了一种用于实现简化状态序列估计的方法和装置，其中使用预先计算（先行）的增加的吞吐量相对于先行深度仅具有线性增加的硬件复杂度。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US20070266069A1

公开(公告)日：2007-11-15

申请号：US11781313

申请日：2007-07-23

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: G06F17/10

CPC classification number: H03H17/06 ,  H03F1/32 ,  H03H2017/0692 ,  H03H2218/06

Abstract: Multi-dimensional finite impulse response filters ale disclosed in hybrid and transpose forms. Multi-dimensional signals can be expressed in a vector (ox matrix) form to allow multi-dimensional signals to be processed collectively. Known hybrid and transpose FIR filters are extended to the multi-dimensional case to allow multi-dimensional signals to be processed with reduced redundancies. The input signals are vectors with multidimensional components. The disclosed FIR filters include multipliers that perform matrix multiplications with multiple coefficients, and adders for performing vector additions with multiple inputs and outputs. The z-transforms are provided for the disclosed hybrid and transpose multi-dimensional FIR filters.

Abstract translation: 混合和转置形式中公开的多维有限脉冲响应滤波器。 多维信号可以以向量（ox矩阵）形式表示，以允许集体处理多维信号。 已知的混合和转置FIR滤波器被扩展到多维情况，以允许以减少的冗余来处理多维信号。 输入信号是具有多维分量的向量。 公开的FIR滤波器包括执行具有多个系数的矩阵乘法的乘法器和用于执行具有多个输入和输出的矢量加法的加法器。 为所公开的混合和转置多维FIR滤波器提供z变换。

公开(公告)号：US07164711B2

公开(公告)日：2007-01-16

申请号：US10348871

申请日：2003-01-22

Applicant: Fuji Yang ,  Fadi Saibi ,  Chunbing Guo ,  Kameran Azadet

Inventor： Fuji Yang ,  Fadi Saibi ,  Chunbing Guo ,  Kameran Azadet

IPC: H03H7/30 ,  H04B3/14

CPC classification number: H04L25/03885

Abstract: A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N≦T.

Abstract translation: 数字可编程模拟接收侧信道均衡器包括级联中的N个相同的零定位（ZP）电路对，其中每对一个ZP电路的传递函数呈现正零，并且另一个ZP电路的传递函数呈现为 负零。 通过数字地控制成对内的可调谐电容器，可以调节均衡器的频率响应和增益，同时保持可控（例如，恒定的）组延迟。 可以选择级联中的块数，并且每个块独立配置，以最佳地补偿广泛传输环境中的高频损耗。 一个实现涉及具有输出抽头的T块级联，其输入T：1输出选择器，使得总均衡器的输出可以被选择为对应于有效长度N的可编程均衡器的任何一个，其中N < T.

公开(公告)号：US07155134B2

公开(公告)日：2006-12-26

申请号：US10219904

申请日：2002-08-15

Applicant: Kameran Azadet

Inventor： Kameran Azadet

IPC: H04B10/06

CPC classification number: H04L25/067 ,  H04B10/503 ,  H04B10/504 ,  H04B10/524 ,  H04B10/58

Abstract: An amplitude modulated optical communication system and method are disclosed that achieve bandwidth compression by making use of an n level amplitude modulation scheme in one or more frequency bands. A soft decision decoder is disclosed that provides at least two soft slicing levels between each signal level in the multiple level transmission scheme to define an “uncertainty” region therebetween. The soft slicing levels are used to evaluate the reliability of a given bit assignment. In addition to assigning a digital value based on the received signal level, one or more soft bits are assigned indicating a “reliability” measure of the output code.

公开(公告)号：US07000175B2

公开(公告)日：2006-02-14

申请号：US09834668

申请日：2001-04-13

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H03M13/03

CPC classification number: H03M13/6331 ,  H03M13/03 ,  H04L25/03057 ,  H04L25/03235 ,  H04L25/4917

Abstract: A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present invention limits the increase in hardware complexity by taking advantage of past decisions (or survivor symbols). The critical path of a conventional RSSE implementation is broken up into at least two smaller critical paths using pipeline registers. Various reduced state sequence estimation implementations are disclosed that employ one-step or multiple-step look-ahead techniques to process a signal received from a dispersive channel having a channel memory.

Abstract translation: 公开了一种用于实现简化状态序列估计的方法和装置，其使用预先计算（先行）来增加吞吐量，相对于先行深度，硬件复杂性仅仅线性增加。 本发明通过利用过去的决定（或幸存者符号）来限制硬件复杂度的增加。 常规RSSE实现的关键路径使用流水线寄存器分解为至少两个较小的关键路径。 公开了各种缩减状态序列估计实现，其采用一步或多步先行技术来处理从具有通道存储器的色散通道接收的信号。

公开(公告)号：US06999521B1

公开(公告)日：2006-02-14

申请号：US09471920

申请日：1999-12-23

Applicant: Kameran Azadet ,  Erich Franz Haratsch

Inventor： Kameran Azadet ,  Erich Franz Haratsch

IPC: H04L5/12

CPC classification number: H04L25/03197 ,  H04L25/03235 ,  H04L25/03299

Abstract: A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes it possible to remove the branch metrics unit and decision-feedback unit from the feedback loop, thereby reducing the critical path. A set of multiplexers select the appropriate branch metrics based on the survivor symbols in the corresponding survivor path cells. The computational load of the precomputations is reduced for multi-dimensional trellis codes by precomputing each dimension of the multi-dimensional trellis code separately. A hybrid survivor memory architecture is also disclosed for a RSSE for a channel having a channel memory of length L, where the survivors corresponding to the L past decoding cycles are stored in a register exchange architecture (REA), and survivors corresponding to later decoding cycles are stored in a trace-back architecture (TBA) or REA.

Abstract translation: 公开了一种用于改进缩减复杂度序列估计技术的处理时间的方法和装置，例如减少的状态序列估计。 预先计算通道存储器中所有可能的符号组合的分支度量可以从反馈回路中去除分支度量单位和决策反馈单元，从而减少关键路径。 一组多路复用器基于相应幸存者路径单元中的幸存者符号来选择适当的分支度量。 通过分别预先计算多维网格码的每个维度，预先计算的计算负荷被减少用于多维网格码。 还公开了用于具有长度为L的信道存储器的信道的RSSE的混合存活器存储器架构，其中对应于L个过去的解码周期的幸存者存储在寄存器交换架构（REA）中，以及对应于稍后的解码周期的幸存者 存储在追溯架构（TBA）或REA中。

公开(公告)号：US20050114554A1

公开(公告)日：2005-05-26

申请号：US10924280

申请日：2004-08-23

Applicant: Kameran Azadet ,  Isaac Livny ,  Anil Mudichintala

Inventor： Kameran Azadet ,  Isaac Livny ,  Anil Mudichintala

IPC: G06F13/14 ,  G06F13/12 ,  G06F13/16 ,  H04L12/24 ,  G06F3/00

CPC classification number: G06F13/128 ,  H04L41/08

Abstract: A peripheral controller is provided for controlling communications with one or more peripheral devices. The peripheral controller includes a controller for controlling one or more peripheral devices; and a single interface to a shared memory device that stores configuration information for at least one of the one or more peripheral devices and additional code, such as boot ROM code. The shared memory device may be, for example, an EEPROM or a serial flash memory device. The controller and shared memory device may optionally communicate using a serial bus to further reduce the pin count. A memory controller maps the user addresses into non-overlapping physical addresses within the shared memory device.

Abstract translation: 提供外围控制器用于控制与一个或多个外围设备的通信。 外围控制器包括用于控制一个或多个外围设备的控制器; 以及与共享存储器设备的单个接口，其存储用于所述一个或多个外围设备中的至少一个以及附加代码（例如引导ROM代码）的配置信息。 共享存储器件可以是例如EEPROM或串行闪存器件。 控制器和共享存储设备可以可选地使用串行总线通信以进一步减少引脚数。 存储器控制器将用户地址映射到共享存储器设备内的非重叠物理地址。

公开(公告)号：US06363112B1

公开(公告)日：2002-03-26

申请号：US09206527

申请日：1998-12-07

Applicant: Kameran Azadet ,  Ming-Lin Yu

Inventor： Kameran Azadet ,  Ming-Lin Yu

IPC: H03K5159

CPC classification number: H04L25/03057 ,  H04L2025/0349

Abstract: A parallel processing decision feedback equalizer is configured to receive a plurality of symbol blocks in parallel via a plurality of corresponding input branches. It is further configured to generate a plurality of decision samples. The equalizer comprises an input buffer for storing calculated decision samples corresponding to at least one previously received symbol block and a plurality of tapped delay calculators coupled to the input buffer and located in each of the input branches which are configured to calculate the first portion of a decision feedback signal corresponding to each input branch based on the impulse response samples and the decision samples stored in said input buffer. A plurality of look-ahead-processors located in each one of the input branches and is coupled to a corresponding one of the tapped delay calculators. Each look-ahead-processor has a depth equal to the sequence order of its corresponding branch so as to calculate all possible components of a decision feedback signal for the corresponding branch. A plurality of selectors are coupled to the look-ahead processors so as to select appropriate ones of the possible components of the decision feedback signal based on decision samples obtained from previous branches.

Abstract translation: 并行处理判决反馈均衡器被配置为经由多个对应的输入分支并行地接收多个符号块。 其还被配置为生成多个决策样本。 均衡器包括用于存储与至少一个先前接收的符号块相对应的计算出的决定样本的输入缓冲器和耦合到输入缓冲器并位于每个输入分支中的多个抽头延迟计算器，其被配置为计算第一部分 基于脉冲响应样本和存储在所述输入缓冲器中的判定样本，对应于每个输入分支的判决反馈信号。多个前视处理器，位于每个输入分支中，并且耦合到相应的一个被敲击 延迟计算器。 每个先行处理器的深度等于其相应分支的序列顺序，以便计算相应分支的判定反馈信号的所有可能分量。 多个选择器被耦合到先行处理器，以便基于从先前分支获得的判定样本来选择判定反馈信号的可能分量中的适当的选择器。