公开(公告)号：US20210134654A1

公开(公告)日：2021-05-06

申请号：US17121726

申请日：2020-12-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/762 ,  H01L23/00 ,  H01L21/84 ,  H01L25/16 ,  H01L25/065 ,  G02F1/017 ,  G02B6/12

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an electromagnetic waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20210134646A1

公开(公告)日：2021-05-06

申请号：US17147320

申请日：2021-01-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; and performing a bonding of a fourth level above the third level, where the fourth level includes a second single crystal layer, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having a same doping type.

公开(公告)号：US20210125852A1

公开(公告)日：2021-04-29

申请号：US17141453

申请日：2021-01-05

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors are horizontally oriented, where the second level is bonded to the first level, where the bonded includes oxide to oxide bonds, where the device includes at least a first logic circuit and a second logic circuit, and where the device includes a control function adapted to use the second logic circuit as a redundancy for the first logic circuit so to overcome a fault in the first logic circuit.

公开(公告)号：US10930608B2

公开(公告)日：2021-02-23

申请号：US17019162

申请日：2020-09-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/02 ,  H01L21/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544

Abstract: A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.

公开(公告)号：US10910364B2

公开(公告)日：2021-02-02

申请号：US16242300

申请日：2019-01-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L27/06 ,  H01L29/812 ,  H01L29/808 ,  H01L27/092 ,  H01L29/732 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/786 ,  H01L29/45 ,  H01L29/423 ,  H01L23/367 ,  H01L27/12 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/02 ,  H01L23/544 ,  H01L23/48 ,  H01L21/84 ,  H01L21/822 ,  H01L21/762 ,  G03F9/00 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/1157 ,  H01L45/00 ,  H01L27/24 ,  H01L27/11524 ,  H01L23/00 ,  H01L27/088 ,  H01L21/268 ,  H01L23/31

Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.

公开(公告)号：US10903089B1

公开(公告)日：2021-01-26

申请号：US17061563

申请日：2020-10-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065 ,  H01L23/373

Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one memory array, wherein said second level comprises at least one Phase Lock Loop (“PLL) circuit, and wherein said third layer comprises crystalline silicon.

公开(公告)号：US10825864B2

公开(公告)日：2020-11-03

申请号：US16409813

申请日：2019-05-11

Applicant: Monolithic 3D Inc.

Inventor： Deepak C. Sekar ,  Zvi Or-Bach

IPC: H01L21/00 ,  H01L27/24 ,  H01L27/22 ,  H01L27/108 ,  H01L21/268 ,  H01L21/683 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11578 ,  H01L27/11551 ,  H01L27/11529 ,  H01L29/423 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/105 ,  H01L45/00

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer; first transistors overlaying the first single crystal layer; second transistors overlaying the first transistors; and a second level including a second single crystal layer, the second level overlays the second transistors, where the first transistors and the second transistors each includes a polysilicon channel.

公开(公告)号：US10811395B2

公开(公告)日：2020-10-20

申请号：US16683244

申请日：2019-11-13

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L21/74 ,  H01L29/66 ,  H01L27/06 ,  H01L23/522 ,  H01L23/485 ,  H01L23/48 ,  H01L21/768 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092 ,  H01L23/00 ,  H01L25/00

Abstract: A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.

公开(公告)号：US20200243423A1

公开(公告)日：2020-07-30

申请号：US16852506

申请日：2020-04-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L27/11551 ,  H01L27/108 ,  H01L29/732 ,  H01L27/11526 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/78 ,  H01L21/74 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

公开(公告)号：US10665695B2

公开(公告)日：2020-05-26

申请号：US16536606

申请日：2019-08-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L29/00 ,  H01L29/12 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66 ,  H01L23/48 ,  H01L23/34 ,  H01L23/50 ,  H01L27/088 ,  H01L27/06 ,  H01L27/02 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11573 ,  H01L23/544 ,  H01L21/74 ,  H01L29/10 ,  H01L29/808 ,  H01L29/732 ,  H01L27/118 ,  H01L27/11578 ,  H01L27/24

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.