公开(公告)号：US20220085974A1

公开(公告)日：2022-03-17

申请号：US17537056

申请日：2021-11-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas ORDAS ,  Yanis LINGE

IPC: H04L9/06 ,  G06F21/72

Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.

公开(公告)号：US20220066494A1

公开(公告)日：2022-03-03

申请号：US17399617

申请日：2021-08-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Demange ,  Nicolas Borrel ,  Jimmy Fort

IPC: G05F3/26 ,  G06F21/75

Abstract: An embodiment electronic circuit power supply device is configured to: flow, through a first conductor connected to a node, a first current that is an image of a second current consumed by the electronic circuit; flow a third current through a second conductor connected to the node; regulate a potential of the node to a constant value by acting on the third current; flow a fourth constant current through a third conductor connected to the node; and consume a fifth current that is an image of the third current.

公开(公告)号：US11265192B2

公开(公告)日：2022-03-01

申请号：US17182957

申请日：2021-02-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yoann Bouvet

IPC: H04L7/00 ,  H04L27/233 ,  H04L27/26 ,  H04L27/00

Abstract: In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

公开(公告)号：US11264324B2

公开(公告)日：2022-03-01

申请号：US16901449

申请日：2020-06-15

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Samuel Boscher ,  Yann Rebours ,  Michel Cuenca

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/522

Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.

公开(公告)号：US11244941B2

公开(公告)日：2022-02-08

申请号：US16877935

申请日：2020-05-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: H01L27/02 ,  H01L23/50

Abstract: A first power supply rail is provided as a power supply tree configured with couplings to distribute a supply voltage to active elements of the circuit. A second power supply rail is provided as an electrostatic discharge channel and is not configured with distribution tree couplings to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power supply rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects another end of the second power supply rail to the first power supply rail at the second electrostatic discharge circuit.

公开(公告)号：US20220038003A1

公开(公告)日：2022-02-03

申请号：US17370609

申请日：2021-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet ,  Didier Davino

IPC: H02M3/158 ,  G05F1/56 ,  H02M1/00 ,  G01R19/00

Abstract: An embodiment electronic device includes a first circuit including first and second transistors series-coupled between a node of application of a power supply voltage and a node of application of a reference voltage, the first and second transistors being coupled to each other by a first node, and a second circuit, configured to compare a first voltage on the first node with first and second voltage thresholds.

公开(公告)号：US20220038001A1

公开(公告)日：2022-02-03

申请号：US17366353

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet ,  Olivier Lauzier

IPC: H02M3/158 ,  H02M1/36 ,  H02M1/00

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.

公开(公告)号：US20220020816A1

公开(公告)日：2022-01-20

申请号：US17489425

申请日：2021-09-29

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Philippe BOIVIN ,  Jean Jacques FAGOT ,  Emmanuel PETITPREZ ,  Emeline SOUCHIER ,  Olivier WEBER

IPC: H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.

公开(公告)号：US11218291B2

公开(公告)日：2022-01-04

申请号：US16281889

申请日：2019-02-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Thomas Ordas ,  Yanis Linge

IPC: H04L9/06 ,  G06F21/72

Abstract: A cryptographic circuit performs a substitution operation of a cryptographic algorithm. For each substitution operation of the cryptographic algorithm, a series of substitution operations are performed by the cryptographic circuit. One of the substitution operations of the series is a real substitution operation corresponding to the substitution operation of the cryptographic algorithm. One or more other substitution operations of the series are dummy substitution operations. A position of the real substitution operation in said series is selected randomly.

公开(公告)号：US20210409030A1

公开(公告)日：2021-12-30

申请号：US17352849

申请日：2021-06-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno GAILHARD ,  Laurent TRUPHEMUS ,  Christophe EVA

IPC: H03L7/10 ,  H03L7/089 ,  H03L7/099

Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.