公开(公告)号：US11321270B2

公开(公告)日：2022-05-03

申请号：US16840759

申请日：2020-04-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G06F13/42 ,  G06F9/30 ,  G06F11/07 ,  G06F13/12 ,  G11C7/10 ,  G11C16/34

Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.

公开(公告)号：US20160141032A1

公开(公告)日：2016-05-19

申请号：US14547199

申请日：2014-11-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois Tailliet

IPC: G11C16/04 ,  G11C29/08 ,  H01L27/115 ,  G11C16/14 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C29/08 ,  G11C29/50004 ,  H01L27/11519 ,  H01L27/11524

Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

Abstract translation: 集成电路存储器包括以行和列排列成阵列的存储单元，每列包括第一位线和第二位线。 每个存储单元由以下部分形成：具有第一源极 - 漏极路径的第一选择晶体管; 具有第二源极 - 漏极路径的第二选择晶体管; 具有第三源极 - 漏极路径的第一浮栅晶体管; 以及具有第四源极 - 漏极路径的第二浮栅晶体管。 第一，第二，第三和第四源极 - 漏极路径串联耦合在第一位线和第二位线之间。 存储器的每行的字线被耦合到第一和第二选择晶体管的栅极端子。 耦合到第一和第二浮栅晶体管的栅极端的每行的控制栅极线。

公开(公告)号：US20140355357A1

公开(公告)日：2014-12-04

申请号：US14293870

申请日：2014-06-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

Abstract: The present disclosure relates to a method for writing in an EEPROM memory, the method comprising steps of: storing the bits of a word to be written in first memory units, erasing a word to be modified, formed by first memory cells connected to a word line and first bit lines, reading bits stored in the memory cells of a word line WL , in a first read mode and storing the bits read in second memory units, reading in a second read mode the bits stored in the memory cells of the word line, and programming each memory cell of the word line connected to a memory unit storing a bit in the programmed state of the word to be written, of an erased word or of a word comprising a bit having different states in the first and second read modes.

Abstract translation: 本发明涉及一种在EEPROM存储器中写入的方法，该方法包括以下步骤：将要写入的字的位存储在第一存储单元中，擦除要连接到字的第一存储器单元形成的要修改的字 行和第一位线，以第一读取模式读取存储在字线WL的存储单元中的位，并存储读入第二存储器单元的位，读取第二读取模式存储在存储器单元中的位 并且将连接到存储单元的字线的每个存储器单元编程为存储要写入的字的编程状态的位的擦除字或包括在第一个中包含不同状态的位的字的字 和第二读取模式。

公开(公告)号：US08654581B2

公开(公告)日：2014-02-18

申请号：US13706132

申请日：2012-12-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C11/34

CPC classification number: G11C5/145 ,  G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/14

Abstract: The disclosure relates to an integrated circuit electrically powered by a supply voltage and comprising a memory electrically erasable and/or programmable by means of a second voltage greater than the supply voltage. The integrated circuit comprises means for receiving the second voltage by the intermediary of a reception terminal of the supply voltage or by the intermediary of a reception or emission terminal of a data or clock signal. Applicable in particular to electronic tags comprising a reduced number of interconnection terminals.

Abstract translation: 本发明涉及一种由电源电压供电并由电存储器电存储和/或可通过大于电源电压的第二电压编程的集成电路。 集成电路包括用于通过电源电压的接收端的中间或通过数据或时钟信号的接收或发射端的中介来接收第二电压的装置。 特别适用于包括减少数量的互连终端的电子标签。

公开(公告)号：US20130094305A1

公开(公告)日：2013-04-18

申请号：US13706152

申请日：2012-12-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C5/14 ,  G11C7/00

CPC classification number: G11C5/145 ,  G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C16/14

Abstract: The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor.

Abstract translation: 本公开涉及一种用于向至少一个集成电路提供用于擦除和/或编程存储器的高电压的装置。 该装置包括与集成电路的至少一个接触端子相连的至少一个接触端子，用于监视由集成电路接收的数据信号并在数据信号中检测存储器的写入命令的监视器，以及用于 当监视器检测到存储器的写入命令时，将高电压施加到集成电路的端子。

公开(公告)号：US10679699B2

公开(公告)日：2020-06-09

申请号：US16048524

申请日：2018-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Roberto Simola

IPC: G11C16/04 ,  H01L27/11517 ,  H01L29/423

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US09514820B2

公开(公告)日：2016-12-06

申请号：US14547199

申请日：2014-11-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/00 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  G11C29/08 ,  G11C16/08 ,  G11C16/10 ,  G11C29/50

CPC classification number: G11C16/0483 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C29/08 ,  G11C29/50004 ,  H01L27/11519 ,  H01L27/11524

Abstract: An integrated circuit memory includes memory cells arranged in an array with rows and columns, each column including a first bit line and a second bit line. Each memory cell is formed by: a first select transistor with a first source-drain path; a second select transistor with a second source-drain path; a first floating gate transistor with a third source-drain path; and a second floating gate transistor with a fourth source-drain path. The first, second, third and fourth source-drain paths are coupled in series between the first bit line and the second bit line. The word line for each row of the memory is coupled to the gate terminals of the first and second select transistors. The control gate line for each row in coupled to the gate terminals of the first and second floating gate transistors.

Abstract translation: 集成电路存储器包括以行和列排列成阵列的存储单元，每列包括第一位线和第二位线。 每个存储单元由以下部分形成：具有第一源极 - 漏极路径的第一选择晶体管; 具有第二源极 - 漏极路径的第二选择晶体管; 具有第三源极 - 漏极路径的第一浮栅晶体管; 以及具有第四源极 - 漏极路径的第二浮栅晶体管。 第一，第二，第三和第四源极 - 漏极路径串联耦合在第一位线和第二位线之间。 存储器的每行的字线被耦合到第一和第二选择晶体管的栅极端子。 耦合到第一和第二浮栅晶体管的栅极端的每行的控制栅极线。

公开(公告)号：US09502110B1

公开(公告)日：2016-11-22

申请号：US14964156

申请日：2015-12-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C11/34 ,  G11C14/00 ,  G11C16/26 ,  G11C11/419

CPC classification number: G11C14/0063 ,  G11C11/412 ,  G11C11/419 ,  G11C16/26

Abstract: A memory cell for use within a memory array includes a memory circuit and a read circuit. The memory circuit includes a non-volatile memory element (for example, a floating gate transistor) coupled to an RS flip flop. The RS flip flop is configured with a p-channel transistor coupled to receive a first enable signal and an n-channel transistor coupled to receive a second enable signal. The assertion of the enable signals is offset in time to control operations for forcing latch nodes to a specific voltage and enabling latching operation. The read circuit includes latch circuit coupled to outputs of the RS flip flop and operable as a sense amplifier circuit. The memory and read circuits are fabricated within a rectangular circuit area. Many such rectangular circuit area may be positioned adjacent to each other in a row or column of the memory array.

Abstract translation: 在存储器阵列中使用的存储单元包括存储器电路和读取电路。 存储电路包括耦合到RS触发器的非易失性存储器元件（例如，浮栅晶体管）。 RS触发器配置有耦合以接收第一使能信号的p沟道晶体管和耦合以接收第二使能信号的n沟道晶体管。 使能信号的断言在时间上偏移以控制用于将锁存器节点强制到特定电压并使能锁存操作的操作。 读取电路包括耦合到RS触发器的输出并可用作读出放大器电路的锁存电路。 存储器和读取电路在矩形电路区域内制造。 许多这样的矩形电路区域可以位于存储器阵列的行或列中彼此相邻的位置。

公开(公告)号：US09390801B2

公开(公告)日：2016-07-12

申请号：US14584165

申请日：2014-12-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois Tailliet

IPC: G11C16/04 ,  G11C16/10 ,  G06F11/20 ,  G11C29/00 ,  G06F11/16 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/10 ,  G06F11/167 ,  G06F11/20 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/3495 ,  G11C29/74

Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.

公开(公告)号：US20150243361A1

公开(公告)日：2015-08-27

申请号：US14632785

申请日：2015-02-26

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet

IPC: G11C16/14

CPC classification number: G11C16/14 ,  G11C16/0433 ,  G11C16/12 ,  G11C16/349 ,  G11C16/3495

Abstract: A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one.

Abstract translation: 一种编程EEPROM的方法，包括：第一模式，其中在第一电压下执行对单元的写入; 以及在小于第一电压的第二电压下执行写入的第二模式。