公开(公告)号：US20140173320A1

公开(公告)日：2014-06-19

申请号：US13717978

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Brijesh Tripathi

IPC: G06F1/12

CPC classification number: G06F1/12 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2330/021 ,  G09G2340/0435 ,  G09G2360/18 ,  G09G2370/047 ,  G09G2370/10

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路，辅助链路和热插拔检测链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令。 源处理器可以经由主链路将初始化参数发送到宿处理器。 初始化参数可以包括时钟数据恢复锁定参数和空闲参数。 在初始化参数之后，源处理器可以经由主链路向宿处理器发送同步信号。 然后，源处理器可以经由主链路向宿处理器发送睡眠命令。

公开(公告)号：US20140168234A1

公开(公告)日：2014-06-19

申请号：US13718142

申请日：2012-12-18

Applicant: APPLE INC.

Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

IPC: G06T1/20

CPC classification number: G09G5/00 ,  G09G5/006

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。

公开(公告)号：US20140085275A1

公开(公告)日：2014-03-27

申请号：US13627885

申请日：2012-09-26

Applicant: APPLE INC.

Inventor： Brijesh Tripathi

IPC: G06F3/038

CPC classification number: G09G5/005 ,  G09G2310/0232 ,  G09G2340/02 ,  G09G2340/0435 ,  G09G2360/121

Abstract: In a graphics system, pixels may be provided to a graphics display at a pixel clock rate corresponding to an actual refresh rate nearest to and lower than a desired/target refresh rate. A number of additional pixels may be provided with the pixels for each image frame. The number is based at least on the actual refresh rate, target refresh rate, and a pixel-resolution of the image frame, such that providing pixels of an image frame and the number of additional pixels for each image frame at the pixel clock rate results in an effective refresh rate matching the target refresh rate. The additional pixels may be provided by adding one or more pixels at the end of each horizontal line of the image frame, or by adding an extra partial line in the vertical blanking interval. The additional pixels are not displayed and do not adversely affect normal operation.

Abstract translation: 在图形系统中，可以以对应于最接近于和低于期望/目标刷新率的实际刷新率的像素时钟速率将像素提供给图形显示。 可以为每个图像帧提供多个附加像素。 该数量至少基于实际刷新率，目标刷新率和图像帧的像素分辨率，使得以像素时钟速率提供每个图像帧的图像帧的像素和附加像素的数量结果 在与目标刷新率匹配的有效刷新率中。 可以通过在图像帧的每条水平线的末端添加一个或多个像素，或者通过在垂直消隐间隔中添加额外的部分线来提供附加像素。 附加像素不显示，不会对正常操作产生不利影响。