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    Digital-to-analog converter system
    1.
    发明授权
    Digital-to-analog converter system 有权
    数模转换器系统

    公开(公告)号：US09374103B1

    公开(公告)日：2016-06-21

    申请号：US14656052

    申请日：2015-03-12

    Applicant: Apple Inc.

    Inventor： Wenbo Liu ,  Raman S. Thiara

    IPC: H03M1/06 ,  H03M1/08 ,  H03K17/16 ,  H03M1/66

    CPC classification number: H03K17/165 ,  H03M1/687 ,  H03M1/76

    Abstract: In some embodiments, a digital-to-analog converter (DAC) system includes an output segment, a main branch, first and second edge segments, and a sub-segment. The output segment includes secondary switches that selectively connect conductive paths to an output. The main branch includes unit resistance elements, each including a resistor and a switch. The first and second edge segments each include a respective group of secondary switches that selectively connect a respective conductive path to a unit resistance element. The sub-segment includes terminal resistors connected to at least one conductive path and includes main switches that selectively connect respective terminal resistors to the unit resistance element. The main switches and the unit resistance element switches use a single switch design. The DAC system may have an improved differential non-linearity (DNL), as compared to a DAC system that does not include the unit resistance element switches or the first and second edge segments.

    Abstract translation: 在一些实施例中，数模转换器（DAC）系统包括输出段，主分支，第一和第二边缘段以及子段。 输出段包括将导电路径选择性地连接到输出的次级开关。 主分支包括单元电阻元件，每个元件包括电阻器和开关。 第一和第二边缘段各自包括相应的一组次级开关，其将相应的导电路径选择性地连接到单位电阻元件。 子段包括连接到至少一个导电路径的端子电阻器，并且包括主开关，其将各个端子电阻器选择性地连接到单位电阻元件。 主开关和单元电阻元件开关采用单开关设计。 与不包括单位电阻元件开关或第一和第二边缘段的DAC系统相比，DAC系统可具有改进的差分非线性（DNL）。

    ELECTRONIC DEVICE FUNCTIONALITY IN LOW POWER MODE
    3.
    发明申请
    ELECTRONIC DEVICE FUNCTIONALITY IN LOW POWER MODE 有权

    公开(公告)号：US20230061200A1

    公开(公告)日：2023-03-02

    申请号：US17464482

    申请日：2021-09-01

    Applicant: Apple Inc.

    Inventor： Langford M. Wasada ,  Arun Unkn ,  Andrew C. Chang ,  Sriram Hariharan ,  Robert W. Brumley ,  Raman S. Thiara

    IPC: G06F1/3206 ,  G06F13/42 ,  H04B17/318

    Abstract: Embodiments disclosed herein relate to reducing a power consumption of an electronic device while maintaining some functionality of the electronic device while the electronic device is in a low power mode. The device may be in the low power mode due to a battery level being below a threshold. If the battery level is below the threshold, the electronic device may enter the low power mode. However, before entering the low power mode, some functionality of an application processor may be transferred to a communication controller. Once the functionality is transferred, the application processor may be disabled to reduce power consumption while maintaining functionality of the application processor. The electronic device may also utilize various communication protocols to communicate with a peripheral device. Even though the electronic device may be in the low power mode, the communication controller may be used to cause the peripheral device to perform various actions.

    Method and apparatus for power glitch detection in integrated circuits
    4.
    发明授权
    Method and apparatus for power glitch detection in integrated circuits 有权
    集成电路中电源毛刺检测的方法和装置

    公开(公告)号：US09541603B2

    公开(公告)日：2017-01-10

    申请号：US13938901

    申请日：2013-07-10

    Applicant: Apple Inc.

    Inventor： Brian S. Park ,  Patrick D. McNamara ,  Kwang M. Lee ,  Meng C. Chong ,  Geertjan Joordens ,  Raman S. Thiara ,  Anh T. Hoang ,  John P. Gonzalez

    IPC: G01R31/00 ,  G01R31/317 ,  G01R19/165 ,  G06F1/28 ,  G01R31/3181

    CPC classification number: G01R31/31721 ,  G01R19/16552 ,  G01R31/31816 ,  G06F1/28

    Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

    Abstract translation: 公开了一种用于IC中电源故障检测的方法和装置。 在一个实施例中，一种方法包括检测电压瞬变的IC中的检测电路，其中电源电压的值至少暂时低于参考电压值。 响应于此，检测电路可以使逻辑值存储在指示检测电路已经检测到低于参考电压的电源电压的寄存器中。 IC可以包括耦合到寄存器的多个检测电路，每个检测电路可以提供检测低于参考电压的电源电压的相应指示。 检测电路可以放置在不同的位置，因此读取寄存器可以产生指示出现这种电压瞬变的位置（如果有的话）的信息。

    MITIGATION OF POWER SUPPLY DISTURBANCE FOR WIRED-LINE TRANSMITTERS
    5.
    发明申请
    MITIGATION OF POWER SUPPLY DISTURBANCE FOR WIRED-LINE TRANSMITTERS 有权
    电力线路变送器供电干扰减轻

    公开(公告)号：US20160062430A1

    公开(公告)日：2016-03-03

    申请号：US14471759

    申请日：2014-08-28

    Applicant: Apple Inc.

    Inventor： Wenbo Liu ,  Raman S. Thiara ,  Shingo Hatanaka

    IPC: G06F1/26 ,  H04L7/08

    CPC classification number: G06F1/266 ,  H04L25/0286 ,  H04L25/03

    Abstract: A wired-line transmitter may include architecture that provides control of the current profile during power-up and/or power-down of the transmitter. The current profile may include a sloped ramp up during power-up and/or a sloped ramp down during power-down. The sloped ramps of the current profile mitigate supply bouncing during power-up and/or power-down. Individual enable signals may be derived from an enable signal provided to the transmitter. These individual enable signals may be provided (or turned off) in a time delayed (e.g., staggered) manner to provide the sloped ramps for the current profile.

    Abstract translation: 有线线路发射机可以包括在发射机的上电和/或掉电期间提供电流分布控制的架构。 电流分布可以包括在上电期间倾斜的斜坡上升和/或掉电期间倾斜的斜坡下降。 当前配置文件的倾斜坡道能够在上电和/或掉电期间缓解供电反弹。 可以从提供给发射机的使能信号导出单独的使能信号。 可以以时间延迟（例如交错）的方式提供（或关闭）这些单独的使能信号，以提供用于当前配置文件的倾斜斜坡。

    Method and Apparatus for Power Glitch Detection in Integrated Circuits
    6.
    发明申请
    Method and Apparatus for Power Glitch Detection in Integrated Circuits 有权
    集成电路中电源毛刺检测的方法与装置

    公开(公告)号：US20150015283A1

    公开(公告)日：2015-01-15

    申请号：US13938901

    申请日：2013-07-10

    Applicant: Apple Inc.

    Inventor： Brian S. Park ,  Patrick D. McNamara ,  Kwang M. Lee ,  Meng C. Chong ,  Geertjan Joordens ,  Raman S. Thiara ,  Anh T. Hoang ,  John P. Gonzalez

    IPC: G01R31/319

    CPC classification number: G01R31/31721 ,  G01R19/16552 ,  G01R31/31816 ,  G06F1/28

    Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

    Abstract translation: 公开了一种用于IC中电源故障检测的方法和装置。 在一个实施例中，一种方法包括检测电压瞬变的IC中的检测电路，其中电源电压的值至少暂时低于参考电压值。 响应于此，检测电路可以使逻辑值存储在指示检测电路已经检测到低于参考电压的电源电压的寄存器中。 IC可以包括耦合到寄存器的多个检测电路，每个检测电路可以提供检测低于参考电压的电源电压的相应指示。 检测电路可以放置在不同的位置，因此读取寄存器可以产生指示出现这种电压瞬变的位置（如果有的话）的信息。

    LOW POWER DISPLAY PORT WITH ARBITRARY LINK CLOCK FREQUENCY
    7.
    发明申请
    LOW POWER DISPLAY PORT WITH ARBITRARY LINK CLOCK FREQUENCY 有权
    低功率显示端口，具有仲裁链路时钟频率

    公开(公告)号：US20140168234A1

    公开(公告)日：2014-06-19

    申请号：US13718142

    申请日：2012-12-18

    Applicant: APPLE INC.

    Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

    IPC: G06T1/20

    CPC classification number: G09G5/00 ,  G09G5/006

    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

    Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。

    Electronic device functionality in low power mode
    8.
    发明授权
    Electronic device functionality in low power mode 有权

    公开(公告)号：US11693467B2

    公开(公告)日：2023-07-04

    申请号：US17464482

    申请日：2021-09-01

    Applicant: Apple Inc.

    Inventor： Langford M. Wasada ,  Arun Unkn ,  Andrew C. Chang ,  Sriram Hariharan ,  Robert W. Brumley ,  Raman S. Thiara

    IPC: G06F1/3206 ,  H04B17/318 ,  G06F13/42 ,  G06F21/44 ,  G06F21/30

    CPC classification number: G06F1/3206 ,  G06F13/4282 ,  G06F21/305 ,  G06F21/44 ,  H04B17/318

    Abstract: Embodiments disclosed herein relate to reducing a power consumption of an electronic device while maintaining some functionality of the electronic device while the electronic device is in a low power mode. The device may be in the low power mode due to a battery level being below a threshold. If the battery level is below the threshold, the electronic device may enter the low power mode. However, before entering the low power mode, some functionality of an application processor may be transferred to a communication controller. Once the functionality is transferred, the application processor may be disabled to reduce power consumption while maintaining functionality of the application processor. The electronic device may also utilize various communication protocols to communicate with a peripheral device. Even though the electronic device may be in the low power mode, the communication controller may be used to cause the peripheral device to perform various actions.

    LINK CLOCK CHANGE DURING VERITCAL BLANKING
    10.
    发明申请
    LINK CLOCK CHANGE DURING VERITCAL BLANKING 有权
    联络时间变化在VERITCAL BLANKING期间

    公开(公告)号：US20140173313A1

    公开(公告)日：2014-06-19

    申请号：US13717941

    申请日：2012-12-18

    Applicant: APPLE INC.

    Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G09G5/00 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  G09G2370/10

    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

    Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。

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