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    Link aggregator for an electronic display
    1.
    发明授权
    Link aggregator for an electronic display 有权

    公开(公告)号：US10699363B2

    公开(公告)日：2020-06-30

    申请号：US15627192

    申请日：2017-06-19

    Applicant: Apple Inc.

    Inventor： Sreeraman Anantharaman ,  Colin Whitby-Strevens

    IPC: G06T1/20 ,  G09G5/00

    Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

    Link aggregator for an electronic display
    5.
    发明授权
    Link aggregator for an electronic display 有权

    公开(公告)号：US09684942B2

    公开(公告)日：2017-06-20

    申请号：US14024428

    申请日：2013-09-11

    Applicant: APPLE INC.

    Inventor： Sreeraman Anantharaman ,  Colin Whitby-Strevens

    IPC: G09G5/00 ,  G06T1/20 ,  H04L25/03 ,  H03H21/00

    CPC classification number: G06T1/20 ,  G09G5/006 ,  G09G2352/00 ,  G09G2370/12

    Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

    METHODS AND APPARATUS FOR LINK TRAINING, INITIALIZATION AND MANAGEMENT VIA A HIGH SPEED BUS INTERFACE
    6.
    发明申请
    METHODS AND APPARATUS FOR LINK TRAINING, INITIALIZATION AND MANAGEMENT VIA A HIGH SPEED BUS INTERFACE 有权
    用于通过高速总线接口进行链接训练，初始化和管理的方法和装置

    公开(公告)号：US20160149654A1

    公开(公告)日：2016-05-26

    申请号：US14550698

    申请日：2014-11-21

    Applicant: Apple Inc.

    Inventor： Colin Whitby-Strevens ,  Brijesh Tripathy

    IPC: H04B17/21

    CPC classification number: H04B17/21 ,  G09G2370/10 ,  H04B1/40 ,  H04B17/0085 ,  H04W24/06 ,  H04W24/08 ,  H04W52/0212

    Abstract: Apparatus and methods for training, initializing, and managing a unidirectional, sink-driven A/V interface of a consumer electronics device. Since camera sensors do not have significant processing capability, the disclosed embodiments couple the camera sensors to a simplified source node as a camera assembly. In the described embodiments, an intelligent receiver (e.g., a master “sink” node) trains, initializes, and manages one or more relatively low complexity camera sensor modules. Various other refinements and simplifications include: (i) where link training is managed by the receiver of the link, not by the transmitter, and (ii) where training multiple links in the network is managed by a single receiver.

    Abstract translation: 用于训练，初始化和管理消费电子设备的单向，水槽驱动的A / V接口的装置和方法。 由于相机传感器不具有显着的处理能力，所公开的实施例将相机传感器耦合到简化的源节点作为相机组件。 在所描述的实施例中，智能接收机（例如，主“宿”节点）训练，初始化和管理一个或多个相对较低复杂度的相机传感器模块。 各种其他改进和简化包括：（i）链路训练由链路的接收机而不是由发射机管理，以及（ii）在网络中训练多个链路由单个接收机管理的地方。

    METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE
    7.
    发明申请
    METHODS AND APPARATUS FOR VIRTUAL CHANNEL ALLOCATION VIA A HIGH SPEED BUS INTERFACE 有权
    通过高速总线接口进行虚拟通道分配的方法和设备

    公开(公告)号：US20150205749A1

    公开(公告)日：2015-07-23

    申请号：US14566454

    申请日：2014-12-10

    Applicant: APPLE INC.

    Inventor： Colin Whitby-Strevens ,  Sreeraman Anantharaman

    IPC: G06F13/42 ,  H04N5/232 ,  H04N1/00

    CPC classification number: G06F13/426 ,  G06F13/4282 ,  G09G5/00 ,  G09G5/006 ,  G09G2340/0435 ,  G09G2352/00 ,  G09G2370/08 ,  G09G2370/10 ,  G09G2370/20 ,  G09G2370/22 ,  H04N5/23203 ,  H04N21/4223 ,  H04N21/426

    Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

    Abstract translation: 电子设备内虚拟信道分配的方法和装置。 在一个示例性实施例中，设备是具有使用修改的高速协议（例如，DisplayPort多流传输（MST）协议））的多个摄像机传感器的消费电子设备经由一个或多个虚拟通道来处理照相机数据。 不同于依赖于智能源设备来管理设备网络的传统解决方案，本公开在一个方面描述了由宿节点（即，“智能宿”）管理的消费电子设备内部节点的网络， 。 另外，由于对于某些设计场景，全套协议（例如，DisplayPort）功能是不必要的，所以某些进一步公开的简化可以改善具有非常适中能力的汇聚节点的性能。

    Methods and apparatus for error rate estimation
    8.
    发明授权
    Methods and apparatus for error rate estimation 有权
    误差率估计方法和装置

    公开(公告)号：US08990645B2

    公开(公告)日：2015-03-24

    申请号：US13897312

    申请日：2013-05-17

    Applicant: Apple Inc.

    Inventor： Colin Whitby-Strevens

    IPC: G06F11/00 ,  G06F11/07 ,  H04L1/00 ,  H04L1/20 ,  G09G3/00 ,  G09G5/00 ,  G09G5/36

    CPC classification number: G06F11/0751 ,  G09G3/006 ,  G09G5/005 ,  G09G5/363 ,  G09G2370/12 ,  H04L1/00 ,  H04L1/0007 ,  H04L1/203

    Abstract: Methods and apparatus for estimating received error rates. In one embodiment, the estimation of received error rates is conducted in relation to a bus interface such as a high-speed High-Definition Multimedia Interface (HDMI) interface, and the method utilizes corrupted symbols that violate TMDS symbol rules, the corrupted symbols being easily detected and counted. In one exemplary implementation, a symbol error rate (SER) can be estimated from the number of detected invalid symbols. The SER can be used to diagnose the performance of the HDMI interface, and optionally as a basis for selecting or implementing corrective action(s).

    Abstract translation: 用于估计接收错误率的方法和装置。 在一个实施例中，对诸如高速高清晰度多媒体接口（HDMI）接口的总线接口进行接收错误率的估计，并且该方法利用违反TMDS符号规则的损坏的符号，损坏的符号是 容易检测和计数。 在一个示例性实现中，可以从检测到的无效符号的数量估计符号错误率（SER）。 SER可用于诊断HDMI接口的性能，并可选择作为选择或实施纠正措施的依据。

    LINK CLOCK CHANGE DURING VERITCAL BLANKING
    9.
    发明申请
    LINK CLOCK CHANGE DURING VERITCAL BLANKING 有权
    联络时间变化在VERITCAL BLANKING期间

    公开(公告)号：US20140173313A1

    公开(公告)日：2014-06-19

    申请号：US13717941

    申请日：2012-12-18

    Applicant: APPLE INC.

    Inventor： Brijesh Tripathi ,  Colin Whitby-Strevens ,  Geertjan Joordens ,  Moon Jung Kim ,  Raman S. Thiara

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G09G5/00 ,  G09G5/006 ,  G09G5/18 ,  G09G2330/021 ,  G09G2370/10

    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

    Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。

    METHODS AND APPARATUS FOR ENSURING COMPATIBILITY ON A HIGH PERFORMANCE SERIAL BUS
    10.
    发明申请
    METHODS AND APPARATUS FOR ENSURING COMPATIBILITY ON A HIGH PERFORMANCE SERIAL BUS 有权
    用于确保高性能串行总线兼容性的方法和装置

    公开(公告)号：US20130058355A1

    公开(公告)日：2013-03-07

    申请号：US13657737

    申请日：2012-10-22

    Applicant: Apple Inc.

    Inventor： Jerrold V. Hauck ,  Colin Whitby-Strevens

    IPC: H04L12/56

    CPC classification number: H04L12/6418 ,  H04L1/0002 ,  H04L12/40052 ,  H04L12/40071

    Abstract: A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.

    Abstract translation: 公开了一种数据通信系统，其具有耦合到至少一个Beta云的至少一个Legacy云。 该系统还具有至少一个BOSS节点和至少一个边界节点。 公开了一种用于确保兼容性的方法，包括确定BOSS节点何时空闲，如果BOSS节点空闲，则确定由任何边界节点发送的最后一个分组是否是Alpha格式分组，如果由 边界节点不是Alpha格式数据包。

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