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公开(公告)号：US20140173313A1
公开(公告)日：2014-06-19
申请号：US13717941
申请日：2012-12-18
Applicant: APPLE INC.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S. Thiara
IPC: G06F1/26
CPC classification number: G06F1/26 , G09G5/00 , G09G5/006 , G09G5/18 , G09G2330/021 , G09G2370/10
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。
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公开(公告)号：US09158350B2
公开(公告)日：2015-10-13
申请号：US13717941
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S Thiara
CPC classification number: G06F1/26 , G09G5/00 , G09G5/006 , G09G5/18 , G09G2330/021 , G09G2370/10
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 接口可以包括主链路和辅助链路。 源处理器可以用于经由辅助链路向宿处理器发送唤醒命令，辅助链路可指示主链路上的频率变化。 通过主链路到宿处理器的源处理器可以发送初始化参数，其可以包括时钟数据恢复锁定参数和空闲参数。
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公开(公告)号：US09013493B2
公开(公告)日：2015-04-21
申请号：US13718142
申请日：2012-12-18
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S Thiara
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。
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公开(公告)号：US20140168234A1
公开(公告)日：2014-06-19
申请号：US13718142
申请日：2012-12-18
Applicant: APPLE INC.
Inventor： Brijesh Tripathi , Colin Whitby-Strevens , Geertjan Joordens , Moon Jung Kim , Raman S. Thiara
IPC: G06T1/20
Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.
Abstract translation: 公开了一种用于实现显示端口接口的设备的实施例。 该装置可以包括通过接口耦合的源处理器和宿处理器。 源处理器可以可操作以从连续的频率范围中选择频率，并且以选定的频率将数据发送到宿处理器。 在宿处理器中可以包括锁相电路。 相位锁定电路可以被配置为根据发送的数据产生所选频率的信号。 产生的信号可以与发送的数据同相。
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