利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

99 条记录 (耗时 0.042 秒)

    Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor
    81.
    发明授权
    Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor 失效
    发送使用DCR命令生成的线程消息指向消息控制块在多处理器中存储消息和响应存储器地址

    公开(公告)号：US07281118B2

    公开(公告)日：2007-10-09

    申请号：US11198042

    申请日：2005-08-05

    申请人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

    发明人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

    IPC分类号： G06F15/167

    CPC分类号： G06F13/28

    摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

    摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

    Method and system for performing asymmetric address translation
    82.
    发明授权
    Method and system for performing asymmetric address translation 失效

    公开(公告)号：US07136385B2

    公开(公告)日：2006-11-14

    申请号：US10017261

    申请日：2001-12-07

    申请人： Philippe Damon ,  Gordon Taylor Davis

    发明人： Philippe Damon ,  Gordon Taylor Davis

    IPC分类号： H04L12/28 ,  H04L12/56

    CPC分类号： H04L61/2514 ,  H04L29/12009 ,  H04L29/12367 ,  H04L29/12462 ,  H04L29/12481 ,  H04L61/255 ,  H04L61/2557

    摘要： A method and system for performing network address translations for a session in a network is disclosed. The network includes at least one local network domain, and the at least one local network domain includes at least one computer system. Each computer system has a local address and is associated with a global address. The session exchanges packets that travel between the computer system within the local network domain and another computer system which may be outside of the local network domain. Each packet includes source and destination information. The method and system include determining a direction of travel for each packet, inbound or outbound, by searching a global address table for a match of a key for each packet. The key is provided using a portion of the destination information. The global address table includes at least one entry. Each entry corresponds to the global address for a first corresponding computer system. The method and system also include asymmetrically translating the source and destination information for each packet using an address translation table or session table based on whether or not the full match is found. The destination information is translated using information in the session table if the packet is inbound. The source information is translated based on the address translation table if the packet is outbound. The address translation table includes at least one entry. Each entry corresponds to the local address for a first corresponding computer system or a global host name for a shared host.

    Connection allocation technology
    83.
    发明授权
    Connection allocation technology 失效
    连接分配技术

    公开(公告)号：US07107344B2

    公开(公告)日：2006-09-12

    申请号：US09931540

    申请日：2001-08-16

    申请人： Gordon Taylor Davis ,  Clark Debs Jeffries ,  Mark Anthony Rinaldi

    发明人： Gordon Taylor Davis ,  Clark Debs Jeffries ,  Mark Anthony Rinaldi

    IPC分类号： G06F15/16

    CPC分类号： H04L69/16 ,  H04L67/14 ,  H04L69/163

    摘要： A method and apparatus useful in network management which makes intelligent, high speed, connection allocation decisions, overcoming difficulties encountered heretofore and providing enhanced network services. During episodes of network congestion, some connection requests for a class of service of low value and with currently a high number of existing connections may be purposefully ignored (not acknowledged with an Acknowledge (ACK) packet) so that the processing capability of a device will not become overwhelmed, causing the dropping of new connection is to note the numbers of connections of different classes relative to their service-level contracts, to ignore abundant, low-value connection requests in accordance with value policies when and only when necessary, and to insure that valuable new connection requests that conform to their contract connection rates can be intelligently accommodated.

    摘要翻译： 一种在网络管理中有用的方法和装置，其实现智能，高速，连接分配决策，克服迄今遇到的困难并提供增强的网络服务。 在网络拥塞发生期间，可以有目的地忽略一些低价值服务和当前具有大量现有连接的连接请求（未被确认（ACK）分组确认），使得设备的处理能力将 不会变得不堪重负，导致新连接的下降是注意到不同类别与其服务级别合同的连接数量，当且仅在必要时根据价值政策忽略丰富的低价值连接请求，并且 确保符合其合同连接率的有价值的新连接请求可以被智能地适应。

    Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache
    84.
    发明授权
    Performance of a cache by including a tag that stores an indication of a previously requested address by the processor not stored in the cache 失效
    缓存的性能包括一个标签，该标签存储未存储在高速缓存中的处理器先前请求的地址的指示

    公开(公告)号：US07010649B2

    公开(公告)日：2006-03-07

    申请号：US10685054

    申请日：2003-10-14

    申请人： Gordon Taylor Davis ,  Thomas Basilio Genduso

    发明人： Gordon Taylor Davis ,  Thomas Basilio Genduso

    IPC分类号： G06F12/08

    CPC分类号： G06F12/126

    摘要： A method and system for improving the performance of a cache. The cache may include a tag entry that identifies the previously requested address by the processor whose data was not located in the cache. If the processor requests that address a second time, then there is a significant probability that the address will be accessed again. When the processor requests the address identified by the tag entry a second time, the cache is updated by inserting the data located at that address and evicting the data located in the least recently used entry. In this manner, data will not be evicted from the cache unless there is a significant probability that the data placed in the cache will likely be accessed again. Hence, data may not be evicted in the cache by the processor and replaced with data that will not be reused, such as in an interrupt routine.

    摘要翻译： 一种用于提高缓存性能的方法和系统。 缓存可以包括标识条目，其标识由数据未位于高速缓存中的处理器先前请求的地址。 如果处理器第二次请求该地址，则重新有可能再次访问该地址。 当处理器第二次请求由标签条目标识的地址时，通过插入位于该地址的数据并驱逐位于最近最少使用的条目中的数据来更新高速缓存。 以这种方式，除非存在可能再次访问高速缓存中的数据的重大概率，否则数据将不会从高速缓存中逐出。 因此，数据可能不会被处理器在高速缓存中驱逐，并且被替换为不被重用的数据，例如在中断程序中。

    System and method for delayed increment of a counter
    85.
    发明授权
    System and method for delayed increment of a counter 失效
    计数器延迟增量的系统和方法

    公开(公告)号：US06996737B2

    公开(公告)日：2006-02-07

    申请号：US10680521

    申请日：2003-10-07

    申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

    IPC分类号： G06F1/04

    CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

    摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

    摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

    Method and system for performing range rule testing in a ternary content addressable memory
    88.
    发明授权
    Method and system for performing range rule testing in a ternary content addressable memory 失效
    在三元内容可寻址存储器中执行范围规则测试的方法和系统

    公开(公告)号：US06886073B2

    公开(公告)日：2005-04-26

    申请号：US10173994

    申请日：2002-06-18

    申请人： Gordon Taylor Davis ,  Clark Debs Jeffries ,  Jan Van Lunteren

    发明人： Gordon Taylor Davis ,  Clark Debs Jeffries ,  Jan Van Lunteren

    IPC分类号： G06F12/00 ,  G06F17/30 ,  H04L29/06

    CPC分类号： H04L69/22 ,  H04L69/12

    摘要： A method and system for storing and searching for prefixes for rules, such as filter rules, in a computer system is disclosed. The method and system include providing a ternary content addressable memory (TCAM). The filter rules use range(s) of values in at least one dimension and correspond to prefix(es). The range(s) are described by prefix(es). Some filter rules may intersect. The method and system include providing priorities for the filter rules. The priorities include at least one different priority for the filter rules that intersect. The method and system also include storing the prefixes in the TCAM in block(s) in an order based upon the priorities of the filter rules. In another aspect, the method and system include searching the TCAM for a longest prefix match for a key and searching an additional storage for an almost exact match for the key in parallel with the TCAM. In this aspect, the method and system include returning the longest prefix match having a lowest or a highest location if the longest prefix match is found in the TCAM and the almost exact match is not found in the additional storage.

    摘要翻译： 公开了一种用于在计算机系统中存储和搜索诸如过滤规则的规则的前缀的方法和系统。 该方法和系统包括提供三元内容可寻址存储器（TCAM）。 过滤器规则使用至少一个维度中的值的范围，并对应于前缀（es）。 范围由前缀（es）描述。 一些过滤规则可能会相交。 该方法和系统包括为过滤规则提供优先级。 优先级至少包含与交叉的过滤规则的一个不同的优先级。 该方法和系统还包括基于过滤器规则的优先级按顺序将块中的前缀存储在块中。 在另一方面，所述方法和系统包括搜索TCAM对于密钥的最长前缀匹配，并且搜索附加存储器以与所述TCM并行的所述密钥几乎精确匹配。 在这方面，如果在TCAM中找到最长前缀匹配并且在附加存储器中找不到几乎精确的匹配，则该方法和系统包括返回具有最低或最高位置的最长前缀匹配。

    Multiple logical interfaces to a shared coprocessor resource
    90.
    发明授权
    Multiple logical interfaces to a shared coprocessor resource 失效
    到共享协处理器资源的多个逻辑接口

    公开(公告)号：US06829697B1

    公开(公告)日：2004-12-07

    申请号：US09656582

    申请日：2000-09-06

    申请人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    发明人： Gordon Taylor Davis ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Mark Anthony Rinaldi

    IPC分类号： G06F1500

    CPC分类号： G06F15/7864

    摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.

    摘要翻译： 嵌入式处理器复合体包含多个协议处理器单元（PPU）。 每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。 每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。 操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。 指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。