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88 条记录 (耗时 0.105 秒)

    Detecting low fidelity sync data
    81.
    发明申请
    Detecting low fidelity sync data 有权
    检测低保真同步数据

    公开(公告)号：US20060028396A1

    公开(公告)日：2006-02-09

    申请号：US10835900

    申请日：2004-04-30

    申请人： Bryan Starbuck ,  David Potter

    发明人： Bryan Starbuck ,  David Potter

    IPC分类号： G09G5/00

    CPC分类号： H04L67/1095 ,  Y10S707/99952

    摘要： The present invention provides for a distributed computing system that is capable of determining when data needs to be synced between two computer devices because data has changed on at least a remote device. More particularly, the present invention provides for a sync adapter that uses sync data to detect that a property on a device is new and needs to synchronize with corresponding data on another machine. The sync data is specific to the two devices in that the sync data mirrors data that was last synchronized between these two computing devices. Other example embodiments use the sync data to detect and mark data as low fidelity data for identifying any date and time information associated with the low fidelity data as potentially unreliable.

    摘要翻译： 本发明提供了一种分布式计算系统，其能够确定何时数据需要在两台计算机设备之间同步，因为数据至少在远程设备上已经改变。 更具体地说，本发明提供一种同步适配器，其使用同步数据来检测设备上的属性是新的，并且需要与另一机器上的相应数据同步。 同步数据特定于两个设备，因为同步数据镜像最后在这两个计算设备之间同步的数据。 其他示例性实施例使用同步数据来检测和标记数据作为低保真度数据，用于将与低保真度数据相关联的任何日期和时间信息识别为潜在不可靠。

    Measurement system including a programmable hardware element and measurement modules that convey interface information
    86.
    发明授权
    Measurement system including a programmable hardware element and measurement modules that convey interface information 有权
    测量系统包括可编程硬件元件和传送接口信息的测量模块

    公开(公告)号：US06823283B2

    公开(公告)日：2004-11-23

    申请号：US10194952

    申请日：2002-07-12

    申请人： Perry Steger ,  Garritt W. Foote ,  David Potter ,  James J. Truchard ,  Hugo A. Andrade ,  Joseph E. Peck ,  Brian Keith Odom

    发明人： Perry Steger ,  Garritt W. Foote ,  David Potter ,  James J. Truchard ,  Hugo A. Andrade ,  Joseph E. Peck ,  Brian Keith Odom

    IPC分类号： G06F300

    CPC分类号： G01D9/005 ,  G06F19/00 ,  G16H40/40

    摘要： System and method for measurement, DAQ, and control operations. A measurement module includes measurement circuitry for performing signal conditioning and/or signal conversion, and interface circuitry which provides an interface for the measurement circuitry. A carrier unit couples to the interface circuitry of the module. A computer system couples to the carrier unit and stores one or more hardware configuration programs. The interface circuitry communicates an interface protocol describing the interface, e.g., to the carrier unit or the computer system. The computer system provides a hardware configuration program in response to the communicated interface protocol, and programs one or more programmable hardware elements on the carrier unit with the hardware configuration program. After being configured, the programmable hardware elements interface with the measurement module in accordance with the communicated interface protocol. The measurement module and the programmed carrier unit may perform together as a DAQ device, measurement device, and/or control device.

    摘要翻译： 测量系统和方法，DAQ和控制操作。 测量模块包括用于执行信号调节和/或信号转换的测量电路以及为测量电路提供接口的接口电路。 载体单元耦合到模块的接口电路。 计算机系统耦合到载体单元并存储一个或多个硬件配置程序。 接口电路将描述接口的接口协议传送到载波单元或计算机系统。 计算机系统响应所传送的接口协议提供硬件配置程序，并且使用硬件配置程序对载波单元上的一个或多个可编程硬件元件进行编程。 配置完成后，可编程硬件元件根据通讯接口协议与测量模块进行接口。 测量模块和编程的载波单元可一起作为DAQ设备，测量设备和/或控制设备执行。

    Reclining chair with guide rail system
    87.
    发明授权
    Reclining chair with guide rail system 失效

    公开(公告)号：US5967609A

    公开(公告)日：1999-10-19

    申请号：US751914

    申请日：1996-11-18

    申请人： David Potter

    发明人： David Potter

    IPC分类号： A47C1/02 ,  A47C1/027 ,  A47C3/02 ,  A47C3/03

    CPC分类号： A47C3/0257 ,  A47C1/027 ,  A47C3/03

    摘要： A reclining chair has a seat structure for supporting a an occupant, a free-standing support assembly for supporting the seat structure, a guided rail system connected to the seat structure and support assembly for allowing an occupant to recline in the seat structure in various positions, and a brake assembly for inhibiting movement of the seat structure. The seat structure includes a frame contoured to comfortably support the occupant. The support assembly includes first and second side members. The guide rail system includes a pair of semi-circular tubular rail members, one rail member connected to opposite sides of the frame, and one or more guide elements mounted to the side members. The frame rotates as the rail members slide through the rail guide brackets, thereby reclining the chair. A preferred brake assembly includes at least one lever actuated brake shoe which engages the rail member, creating sufficient friction to inhibit movement of the rail member through the guide elements, thereby fixing the seat structure and occupant the desired reclining position. An alternate brake assembly inhibits movement of the seat portion through the use of a switch activated linear locking mechanism.

    Distributed arbitration circuitry for data processing system
    88.
    发明授权
    Distributed arbitration circuitry for data processing system 失效
    数据处理系统的分布式仲裁电路

    公开(公告)号：US4229791A

    公开(公告)日：1980-10-21

    申请号：US954456

    申请日：1978-10-25

    申请人： John V. Levy ,  David Rodgers ,  Robert E. Stewart ,  David Potter ,  Richard J. Casabona

    发明人： John V. Levy ,  David Rodgers ,  Robert E. Stewart ,  David Potter ,  Richard J. Casabona

    IPC分类号： G06F13/26 ,  G06F13/378 ,  G06F9/46

    CPC分类号： G06F13/378 ,  G06F13/26

    摘要： A digital data processing system including an interconnection for the various elements that constitute the system. Each element that connects to the interconnection is called a nexus, and each nexus in the system can communicate with other nexuses on a priority basis. A central clocking circuit generates timing signals that control such communications by defining bus cycles on a synchronous basis and each nexus contains priority circuitry that operates in response to these signals. Each nexus that requires access to the interconnection asserts a transfer request signal at a predetermined time during each bus cycle. Priority arbitration circuitry in each nexus receives all such requests and samples them at another, later, time during each bus cycle. When a nexus is transmitting a request and no nexus with a higher priority is transmitting a request, that nexus takes control of the interconnection. A transfer during a subsequent bus cycle to another nexus can be prevented during certain types of transfers.

    摘要翻译： 数字数据处理系统，包括构成系统的各种元件的互连。 连接到互连的每个元素称为连接，系统中的每个连接可以优先与其他连接进行通信。 中央时钟电路产生通过在同步基础上定义总线周期来控制这种通信的定时信号，并且每个连接线包含响应于这些信号而操作的优先电路。 需要访问互连的每个连接在每个总线周期期间的预定时间断言传送请求信号。 每个连接中的优先级仲裁电路在每个总线周期的另一个时间段接收所有这些请求并对它们进行采样。 当一个连接正在发送一个请求时，没有更高优先级的连接正在发送一个请求，那个连接就控制了互连。 在某些类型的传输期间，可以防止在后续总线周期到另一个连接的传输。