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89 条记录 (耗时 0.054 秒)

    Control of bottom dimension of tapered contact via variation(s) of etch process
    81.
    发明授权
    Control of bottom dimension of tapered contact via variation(s) of etch process 有权
    通过蚀刻工艺的变化控制锥形接触件的底部尺寸

    公开(公告)号：US07186650B1

    公开(公告)日：2007-03-06

    申请号：US10909509

    申请日：2004-08-02

    申请人： Srikanteswara Dakshina-Murthy

    发明人： Srikanteswara Dakshina-Murthy

    IPC分类号： H01L21/66 ,  H01L21/302 ,  H01L21/461 ,  H01L21/311

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/76816 ,  H01L22/26

    摘要： Systems and methods are described for controlling critical dimension (CD) variation at the bottom of a tapered contact via on a semiconductor substrate. The invention monitors contact vias on a wafer to detect variations in CD at the top of the via in order to facilitate selective alteration of etching component ratios in an etching process, which permits adjustment of the slope of the tapered contact vias. In this manner, the invention compensates for top CD variations to maintain desired CD at the bottom of tapered vias within a target tolerance on subsequent wafers in a wafer fabrication environment.

    摘要翻译： 描述了用于控制半导体衬底上锥形接触通孔底部的临界尺寸（CD）变化的系统和方法。 本发明监测晶片上的接触通孔以检测通孔顶部的CD的变化，以便促进在蚀刻过程中选择性地改变蚀刻成分比，这允许调节锥形接触通孔的斜率。 以这种方式，本发明补偿了顶部CD变化，以在晶圆制造环境中的后续晶片的目标公差内将期望的CD保持在锥形通孔的底部。

    Method of forming isolation trench with spacer formation
    82.
    发明授权
    Method of forming isolation trench with spacer formation 有权
    形成隔离沟的方法

    公开(公告)号：US07144785B2

    公开(公告)日：2006-12-05

    申请号：US10976869

    申请日：2004-11-01

    申请人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Mark C. Kelling ,  Asuka Nomura

    发明人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Mark C. Kelling ,  Asuka Nomura

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76224

    摘要： A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.

    摘要翻译： 具有浅沟槽隔离（STI）结构的应变硅半导体装置具有在硅锗（SiGe）层上形成的应变硅（Si）层。 沟槽穿过Si层延伸到SiGe层中，并且采用覆盖SiGe层中的沟槽内的整个侧壁的侧壁间隔物。 在STI填充，抛光和氮化物剥离工艺步骤之后，可以进行进一步处理，而不用关心SiGe层暴露于硅化物形成过程。

    Method for forming rectangular-shaped spacers for semiconductor devices
    84.
    发明授权
    Method for forming rectangular-shaped spacers for semiconductor devices 有权
    用于形成用于半导体器件的矩形间隔件的方法

    公开(公告)号：US07022596B2

    公开(公告)日：2006-04-04

    申请号：US10747680

    申请日：2003-12-30

    申请人： Huicai Zhong ,  Srikanteswara Dakshina-Murthy

    发明人： Huicai Zhong ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L29/6656

    摘要： A semiconductor device and method of making the same forms a spacer by depositing a spacer layer over a substrate and a gate electrode and forms a protective layer on the spacer layer. The protective layer is dry etched to leave a thin film sidewall on the spacer layer. The spacer layer is then etched, with the protective layer protecting the outer sidewalls of the spacer layer. This etching creates spacers on the gate that have substantially vertical sidewalls that extend parallel to the gate electrode sidewalls. The I-shape of the spacers prevent punch-through during the source/drain ion implantation process, providing an improved source/drain implant dose profile.

    摘要翻译： 半导体器件及其制造方法通过在衬底和栅电极上沉积间隔层形成间隔物并在间隔层上形成保护层。 干蚀刻保护层以在间隔层上留下薄膜侧壁。 然后蚀刻间隔层，其中保护层保护间隔层的外侧壁。 该蚀刻在栅极上产生具有平行于栅电极侧壁延伸的基本垂直侧壁的间隔物。 间隔物的I形形状在源/漏离子注入过程中防止穿通，从而提供改进的源极/漏极注入剂量分布。

    Narrow fin FinFET
    86.
    发明授权
    Narrow fin FinFET 有权
    窄鳍FinFET

    公开(公告)号：US06762483B1

    公开(公告)日：2004-07-13

    申请号：US10348910

    申请日：2003-01-23

    申请人： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

    发明人： Zoran Krivokapic ,  Judy Xilin An ,  Srikanteswara Dakshina-Murthy ,  Haihong Wang ,  Bin Yu

    IPC分类号： H01L2906

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66818 ,  H01L29/78687

    摘要： A method of forming fins for a double-gate fin field effect transistor (FinFET) includes forming a second layer of semi-conducting material over a first layer of semi-conducting material and forming double caps in the second layer of semi-conducting material. The method further includes forming spacers adjacent sides of each of the double caps and forming double fins in the first semi-conducting material beneath the double caps. The method also includes thinning the double fins to produce narrow double fins.

    摘要翻译： 一种形成双栅极鳍效应晶体管（FinFET）的鳍片的方法包括在第一半导体材料层上形成第二半导电材料层，并在第二半导体材料层中形成双重盖子。 该方法还包括在每个双盖的侧面上形成间隔物，并在双盖下方的第一半导体材料中形成双翅片。 该方法还包括使双翅片变薄以产生窄的双翅片。

    Method for formation of a differential offset spacer
    87.
    发明授权
    Method for formation of a differential offset spacer 有权
    形成差动偏移间隔物的方法

    公开(公告)号：US06696334B1

    公开(公告)日：2004-02-24

    申请号：US10260485

    申请日：2002-09-30

    申请人： Kay Hellig ,  Srikanteswara Dakshina-Murthy ,  Christoph Schwan

    发明人： Kay Hellig ,  Srikanteswara Dakshina-Murthy ,  Christoph Schwan

    IPC分类号： H01L218238

    CPC分类号： H01L21/823864

    摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.

    摘要翻译： 提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。 该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。 形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。 然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。 在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。 端点用于停止间隔物蚀刻工艺。

    Metal gate stack with etch stop layer
    88.
    发明授权
    Metal gate stack with etch stop layer 有权
    具有蚀刻停止层的金属栅极叠层

    公开(公告)号：US06664604B1

    公开(公告)日：2003-12-16

    申请号：US10273306

    申请日：2002-10-18

    申请人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    发明人： Paul R. Besser ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2144

    CPC分类号： H01L21/28088 ,  H01L29/4966

    摘要： A metal gate structure and method of forming the same employs an etch stop layer between a first metal layer, made of TiN, for example, and the metal gate formed of tungsten. The etch stop layer prevents overetching of the TiN during the etching of the tungsten in the formation of the metal gate. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum in the etch stop layer allows a thin etch stop layer to be used that provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.

    摘要翻译： 金属栅极结构及其形成方法采用例如由TiN制成的第一金属层和由钨形成的金属栅之间的蚀刻停止层。 蚀刻停止层防止在形成金属栅极期间钨蚀刻期间TiN的过蚀刻。 防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。 在蚀刻停止层中提供铝或钽允许使用薄的蚀刻停止层，其提供足够的蚀刻停止能力并且不会不期望地影响TiN的功函数。