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公开(公告)号：US06696334B1
公开(公告)日：2004-02-24
申请号：US10260485
申请日：2002-09-30
IPC分类号： H01L218238
CPC分类号： H01L21/823864
摘要： A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.
摘要翻译： 提出了一种适用于掺入高级CMOS技术设备的制造工艺中的差分偏移间隔物形成方法。 该方法包括形成覆盖多个栅极结构的第一绝缘层，然后形成覆盖第一绝缘层的第二绝缘层。 形成掩模以暴露覆盖第一晶体管类型的栅极结构的第二绝缘层的第一部分，并且保护覆盖第二晶体管类型的晶体管的栅极结构的第二绝缘层的第二部分。 然后蚀刻覆盖第一类型的栅极结构的第二绝缘层的暴露的第一部分。 在蚀刻之后，去除掩模，并且蚀刻第二绝缘层和第一绝缘层的暴露的第二部分以形成邻接栅极结构的差分间隔物。 端点用于停止间隔物蚀刻工艺。
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2.发明授权公开(公告)号：US06673635B1
公开(公告)日：2004-01-06
申请号：US10185780
申请日：2002-06-28
IPC分类号： H01L2100
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
摘要翻译： 提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。 具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。
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3.发明授权Method for forming alignment features and back-side contacts with fewer lithography and etch steps 有权用较少光刻和蚀刻步骤形成对准特征和背面接触的方法公开(公告)号：US06979651B1
公开(公告)日：2005-12-27
申请号：US10207653
申请日：2002-07-29
IPC分类号： H01L21/308 , H01L21/311 , H01L21/762 , H01L23/544
CPC分类号： H01L21/76264 , H01L21/3081 , H01L21/31144 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.
摘要翻译： 该方法执行第一次光刻和蚀刻，以将浅沟槽隔离特征和对准标记特征形成到顶部SOI层中。 然后用介电材料填充浅沟槽以形成隔离。 然后施加第二光刻和蚀刻步骤以蚀刻用于背面接触的窗口位置，并将对准标记向下转移到SOI下基板中。 在该第一光刻和蚀刻步骤之后，顶部硅中的对准标记可用于对准第二光刻掩模和蚀刻。 这可以通过将抛光停止层留在晶片上来实现，其用于增加对准标记图案的光学有效厚度。 在第二次蚀刻工艺之后去除抛光停止层。 该教导可以应用于任何半导体绝缘体型晶片/技术，其中顶部半导体层不比最佳对准标记深度厚。
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4.发明授权Method for enhancing shallow trench top corner rounding using endpoint control of nitride layer etch process with appropriate etch front 失效使用适当蚀刻前沿的氮化物层蚀刻工艺的端点控制来增强浅沟槽顶角圆角的方法公开(公告)号：US06579801B1
公开(公告)日：2003-06-17
申请号：US09997986
申请日：2001-11-30
IPC分类号： H01L21311
CPC分类号： H01L21/31116 , H01L21/3065 , H01L21/3083 , H01L21/76232
摘要： Various methods of fabricating substrate trenches and isolation structures therein are disclosed. In one aspect, a method of fabricating a trench in a substrate is provided. An oxide/nitride stack is formed on the substrate. An opening with opposing sidewalls is plasma etched in the silicon nitride film until a first portion of the oxide film is exposed while second and third portions of the oxide film positioned on opposite sides of the first portion remain covered by first and second portions of the silicon nitride film that project inwardly from the opposing sidewalls. The oxide film is etched for a selected time period in order to expose a portion of the substrate and to define first and second oxide/nitride ledges that project inwardly from the opposing sidewalls. The substrate is etched to form the trench with the first and second oxide/nitride ledges protecting underlying portions of the substrate.
摘要翻译： 公开了在其中制造衬底沟槽和隔离结构的各种方法。 一方面，提供了在衬底中制造沟槽的方法。 在基板上形成氧化物/氮化物堆叠。 具有相对的侧壁的开口在氮化硅膜中被等离子体蚀刻，直到氧化膜的第一部分暴露，而位于第一部分的相对侧上的氧化膜的第二和第三部分保持被硅的第一和第二部分覆盖 氮化物膜从相对的侧壁向内突出。 在选择的时间段内蚀刻氧化膜以暴露衬底的一部分并且限定从相对的侧壁向内突出的第一和第二氧化物/氮化物凸缘。 蚀刻衬底以与保护衬底下部的第一和第二氧化物/氮化物凸缘形成沟槽。
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5.发明授权公开(公告)号：US08547521B1
公开(公告)日：2013-10-01
申请号：US11000653
申请日：2004-12-01
CPC分类号： G03F7/70891 , G03F7/70341
摘要： The subject invention provides systems and methods that monitor and/or control turbulence of an immersion medium. The systems and methods relate to computer controlled techniques that reduce effects of immersion medium flow due to a liquid temperature gradient. According to an aspect of the subject invention, a number of temperature measurements of the immersion medium are obtained, and the temperature measurements are utilized to generate a gradient map of the immersion medium. By way of illustration, the temperature measurements can be made via wireless temperature sensors. The gradient map can be utilized to understand the stability of the immersion medium. According to an aspect of the subject invention, instability identified with the gradient map can be mitigated.
摘要翻译： 本发明提供了监测和/或控制浸没介质的湍流的系统和方法。 这些系统和方法涉及由于液体温度梯度而降低浸没介质流动影响的计算机控制技术。 根据本发明的一个方面，获得浸渍介质的多个温度测量值，并利用温度测量值来产生浸渍介质的梯度图。 作为说明，可以通过无线温度传感器进行温度测量。 梯度图可用于了解浸没介质的稳定性。 根据本发明的一个方面，可以减轻用梯度图识别的不稳定性。
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公开(公告)号：US07737021B1
公开(公告)日：2010-06-15
申请号：US10261613
申请日：2002-09-30
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas John Kepler
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.
摘要翻译： 本发明涉及一种形成半导体器件的方法。 在一个说明性实施例中，该方法包括在形成在电介质材料层上方的光致抗蚀剂层中限定具有第一尺寸的光致抗蚀剂特征。 该方法还包括减小光致抗蚀剂特征的第一尺寸以产生减小尺寸的光致抗蚀剂特征，在减小尺寸的光致抗蚀剂特征下的电介质材料层中形成开口，以及在电介质材料层中的开口中形成导电材料 。
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公开(公告)号：US20080283878A1
公开(公告)日：2008-11-20
申请号：US11750473
申请日：2007-05-18
IPC分类号： H01L23/482 , H01L21/4763 , H01L29/772 , H01L29/78 , H01L21/66
CPC分类号： H01L21/28035 , H01L22/20 , H01L22/34 , H01L29/78
摘要： Various apparatus and methods of monitoring endcap pullback are disclosed. In one aspect, an apparatus is provided that includes a substrate that has a plurality of semiconductor regions. Each of the plurality of semiconductor regions has a border with an insulating structure. A transistor is positioned in each of the plurality of semiconductor regions. Each of the transistors includes a gate that has a first lateral dimension and an end that has a position relative to its border. A voltage source is electrically coupled to the transistors whereby levels of currents flowing through the transistors are indicative of the positions of the ends of the gates relative to their borders.
摘要翻译： 公开了监测端帽回退的各种装置和方法。 一方面，提供了一种包括具有多个半导体区域的基板的装置。 多个半导体区域中的每一个具有与绝缘结构的边界。 晶体管位于多个半导体区域的每一个中。 每个晶体管包括具有第一横向尺寸的门和具有相对于其边界的位置的端部。 电压源电耦合到晶体管，因此流过晶体管的电流水平指示栅极的端部相对于其边界的位置。
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公开(公告)号：US07386162B1
公开(公告)日：2008-06-10
申请号：US10874498
申请日：2004-06-23
IPC分类号： G06K9/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00 , H01L21/67242
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate compensating for imprint mask critical dimension error(s). An aspect of the invention generates feedback information that facilitates control of imprint mask critical dimension via employing a scatterometry system to detect imprint mask critical dimension error, and mitigating the error via a spacer etchback procedure.
摘要翻译： 本发明一般涉及光刻系统和方法，更具体地涉及有助于补偿压印掩模临界尺寸误差的系统和方法。 本发明的一个方面产生反馈信息，其通过使用散射测量系统来检测压印掩模临界尺寸误差并通过间隔回蚀程序来减轻误差，从而有助于控制压印掩模临界尺寸。
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公开(公告)号：US07376259B1
公开(公告)日：2008-05-20
申请号：US10874499
申请日：2004-06-23
IPC分类号： G06K9/00
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that modify an imprint mask. An aspect of the invention generates feedback information that facilitates control of imprint mask feature height via employing a scatterometry system to detect topography variation and, decreasing imprint mask feature height in order to compensate for topography variation.
摘要翻译： 本发明一般涉及光刻系统和方法，更具体地涉及修改压印掩模的系统和方法。 本发明的一个方面产生反馈信息，其通过使用散射测量系统来检测地形变化和减小压印掩模特征高度以便补偿地形变化，从而有助于控制印迹掩模特征高度。
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公开(公告)号：US06833588B2
公开(公告)日：2004-12-21
申请号：US10274867
申请日：2002-10-22
申请人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
IPC分类号： H01L2701
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66795 , H01L29/66803
摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.
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