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81.发明授权Processor, data processing system and method for synchronizing access to data in shared memory 失效处理器，数据处理系统和方法，用于同步共享存储器中数据的访问公开(公告)号：US07475191B2
公开(公告)日：2009-01-06
申请号：US11195021
申请日：2005-08-02
申请人： Guy L. Guthrie , Derek E. Williams
发明人： Guy L. Guthrie , Derek E. Williams
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： A processing unit for a multiprocessor data processing system includes a processor core and a lower level cache including a reservation logic that records reservations of the processor core. The reservation logic passes or fails store-conditional operations received from the processor core based upon whether the processor core has reservations for target store addresses of the store-conditional operations. The processor core includes a store-through upper level cache, a reservation register, and sequencer logic that, by reference to the reservation register, fails a store-conditional operation without communication with said reservation logic.
摘要翻译： 一种用于多处理器数据处理系统的处理单元包括处理器核心和包含记录处理器核心预约的预约逻辑的下级高速缓存。 基于处理器核心是否具有对存储条件操作的目标存储地址的预留，预留逻辑通过或失败从处理器核心接收的存储条件操作。 处理器核心包括通过存储的上级缓存，预约寄存器和定序器逻辑，其通过参考预约寄存器而失败存储条件操作，而不与所述预留逻辑通信。
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82.发明授权Data processing system and method in which a participant initiating a read operation protects data integrity 失效数据处理系统和方法，其中发起读取操作的参与者保护数据完整性公开(公告)号：US07984256B2
公开(公告)日：2011-07-19
申请号：US11250022
申请日：2005-10-13
CPC分类号： G06F12/0831 , G06F12/0815 , G06F12/0824
摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.
摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。
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83.发明申请公开(公告)号：US20100235584A1
公开(公告)日：2010-09-16
申请号：US12402025
申请日：2009-03-11
申请人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/12 , G06F12/128
摘要： A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.
摘要翻译： 选择具有数据无效相干状态的受害者缓存线，用于从第一处理单元的第一较低级缓存进行舍入。 第一处理单元在互连结构上发出用于标识要从第一较低级高速缓存丢弃的受害缓存行的横向聚合（LCO）命令，指示数据无效相干状态，并指示较低级别高速缓存是预期目的地 的受害者缓存行。 响应于指示LCO命令成功的LCO命令的一致性响应，从第一低级缓存中移除受害者高速缓存行并将其保存在数据无效一致状态中的第二处理单元的第二较低级高速缓存中。
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84.发明授权公开(公告)号：US08949540B2
公开(公告)日：2015-02-03
申请号：US12402025
申请日：2009-03-11
申请人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
发明人： Guy L. Guthrie , Hien M. Le , Alvan W. Ng , Michael S. Siegel , Derek E. Williams , Phillip G. Williams
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F12/12 , G06F12/128
摘要： A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.
摘要翻译： 选择具有数据无效相干状态的受害者缓存线，用于从第一处理单元的第一较低级缓存进行舍入。 第一处理单元在互连结构上发出用于标识要从第一较低级高速缓存丢弃的受害缓存行的横向聚合（LCO）命令，指示数据无效相干状态，并指示较低级别高速缓存是预期目的地 的受害者缓存行。 响应于指示LCO命令成功的LCO命令的一致性响应，从第一低级缓存中移除受害者高速缓存行并将其保存在数据无效一致状态中的第二处理单元的第二较低级高速缓存中。
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公开(公告)号：US20130205099A1
公开(公告)日：2013-08-08
申请号：US13368987
申请日：2012-02-08
申请人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Jeff A. Stuecheli , Derek E. Williams
发明人： Guy L. Guthrie , Hien M. Le , Hugh Shen , Jeff A. Stuecheli , Derek E. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1008 , G06F2212/1016
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.
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86.发明申请公开(公告)号：US20130205098A1
公开(公告)日：2013-08-08
申请号：US13368958
申请日：2012-02-08
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811
摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.
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87.发明授权Barriers processing in a multiprocessor system having a weakly ordered storage architecture without broadcast of a synchronizing operation 失效在具有弱排序存储体系结构的多处理器系统中进行障碍处理，而无需广播同步操作公开(公告)号：US08095739B2
公开(公告)日：2012-01-10
申请号：US12422698
申请日：2009-04-13
IPC分类号： G06F13/00
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. A request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 在最后一个杀死型命令时，对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分进行更新的请求在第一处理单元处于等待状态，第一处理的高速缓存层级 单元允许仅在至少一个杀死型命令完成之后将更新暴露给任何第一处理器核。
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88.发明申请Barriers Processing in a Multiprocessor System Having a Weakly Ordered Storage Architecture Without Broadcast of a Synchronizing Operation 失效具有弱序列存储架构的多处理器系统中的障碍处理，无需广播同步操作公开(公告)号：US20100262786A1
公开(公告)日：2010-10-14
申请号：US12422698
申请日：2009-04-13
CPC分类号： G06F12/0897 , G06F12/0815 , G06F12/0862 , G06F12/126
摘要： A data processing system employing a weakly ordered storage architecture includes first and second sets of processing units coupled to each other and data storage by an interconnect fabric. Each processing unit has a processor core having an associated cache hierarchy including at least a level one, level two and level three cache memories. In response to a request to perform an update to a portion of a first image of memory contained in the level three cache memory of a first processing unit while at last one kill-type command is pending at the first processing unit, the cache hierarchy of the first processing unit permitting the update to be exposed to any first processor core only after the at least one kill-type command is complete.
摘要翻译： 采用弱有序存储架构的数据处理系统包括彼此耦合的第一和第二组处理单元以及互连结构的数据存储。 每个处理单元具有处理器核心，其具有包括至少一级，二级和三级高速缓冲存储器的相关联的高速缓存层级。 响应于对包含在第一处理单元的三级高速缓冲存储器中的存储器的第一图像的一部分执行更新的请求，而最后一个杀死型命令在第一处理单元处于等待状态，则高速缓存层级 所述第一处理单元仅在所述至少一个杀死型命令完成之后允许所述更新暴露于任何第一处理器核心。
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公开(公告)号：US08296519B2
公开(公告)日：2012-10-23
申请号：US12650961
申请日：2009-12-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
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90.发明申请SYNCHRONIZING ACCESS TO DATA IN SHARED MEMORY VIA UPPER LEVEL CACHE QUEUING 失效通过上级缓存队列同步访问共享存储器中的数据公开(公告)号：US20110161590A1
公开(公告)日：2011-06-30
申请号：US12650961
申请日：2009-12-31
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3834
摘要： A processing unit includes a store-in lower level cache having reservation logic that determines presence or absence of a reservation and a processor core including a store-through upper level cache, an instruction execution unit, a load unit that, responsive to a hit in the upper level cache on a load-reserve operation generated through execution of a load-reserve instruction by the instruction execution unit, temporarily buffers a load target address of the load-reserve operation, and a flag indicating that the load-reserve operation bound to a value in the upper level cache. If a storage-modifying operation is received that conflicts with the load target address of the load-reserve operation, the processor core sets the flag to a particular state, and, responsive to execution of a store-conditional instruction, transmits an associated store-conditional operation to the lower level cache with a fail indication if the flag is set to the particular state.
摘要翻译： 处理单元包括具有确定存在或不存在预留的预约逻辑的存储下位缓存和包括存储通过上级缓存，指令执行单元，负载单元的处理器核心，该负载单元响应于 由指令执行单元通过执行装载预约指令而产生的加载备用操作的上级缓存暂时缓冲加载备用操作的加载目标地址，以及指示载入预约操作被绑定到 上级缓存中的值。 如果接收到与加载保留操作的加载目标地址冲突的存储修改操作，则处理器核心将该标志设置为特定状态，并且响应于执行存储条件指令，发送关联的存储 - 如果该标志被设置为特定状态，则向低级缓存进行条件操作，并显示故障指示。
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