公开(公告)号：US08793442B2

公开(公告)日：2014-07-29

申请号：US13368958

申请日：2012-02-08

申请人： Guy L Guthrie ,  Hien M Le ,  Jeff A Stuecheli ,  Derek E Williams

发明人： Guy L Guthrie ,  Hien M Le ,  Jeff A Stuecheli ,  Derek E Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

摘要翻译： 多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。 响应于高速缓冲存储器检测指定与由高速缓冲存储器处理的第一读取型操作相同的目标地址的存储修改操作，高速缓冲存储器为存储修改操作提供重试响应。 响应于完成读取型操作，缓存存储器进入裁判模式。 在裁判模式下，高速缓存存储器临时动态地增加针对目标地址的任何存储修改操作的优先级，这相对于针对目标地址的任何第二读取类型操作。

公开(公告)号：US08949540B2

公开(公告)日：2015-02-03

申请号：US12402025

申请日：2009-03-11

申请人： Guy L. Guthrie ,  Hien M. Le ,  Alvan W. Ng ,  Michael S. Siegel ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  Hien M. Le ,  Alvan W. Ng ,  Michael S. Siegel ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/12 ,  G06F12/128

摘要： A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.

摘要翻译： 选择具有数据无效相干状态的受害者缓存线，用于从第一处理单元的第一较低级缓存进行舍入。 第一处理单元在互连结构上发出用于标识要从第一较低级高速缓存丢弃的受害缓存行的横向聚合（LCO）命令，指示数据无效相干状态，并指示较低级别高速缓存是预期目的地 的受害者缓存行。 响应于指示LCO命令成功的LCO命令的一致性响应，从第一低级缓存中移除受害者高速缓存行并将其保存在数据无效一致状态中的第二处理单元的第二较低级高速缓存中。

公开(公告)号：US08799588B2

公开(公告)日：2014-08-05

申请号：US13368987

申请日：2012-02-08

申请人： Guy L Guthrie ,  Hien M Le ,  Hugh Shen ,  Jeff A Stuecheli ,  Derek E Williams

发明人： Guy L Guthrie ,  Hien M Le ,  Hugh Shen ,  Jeff A Stuecheli ,  Derek E Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F2212/1008 ,  G06F2212/1016

摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.

公开(公告)号：US20130205099A1

公开(公告)日：2013-08-08

申请号：US13368987

申请日：2012-02-08

申请人： Guy L. Guthrie ,  Hien M. Le ,  Hugh Shen ,  Jeff A. Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hien M. Le ,  Hugh Shen ,  Jeff A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/1008 ,  G06F2212/1016

摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. The cache memory issues a read-type operation for a target cache line. While waiting for receipt of the target cache line, the cache memory monitors to detect a competing store-type operation for the target cache line. In response to receiving the target cache line, the cache memory installs the target cache line in the cache memory, and sets a coherency state of the target cache line installed in the cache memory based on whether the competing store-type operation is detected.

公开(公告)号：US20130205098A1

公开(公告)日：2013-08-08

申请号：US13368958

申请日：2012-02-08

申请人： Guy L. Guthrie ,  Hien M. Le ,  Jeff A. Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hien M. Le ,  Jeff A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/0811

摘要： A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

公开(公告)号：US20100100786A1

公开(公告)日：2010-04-22

申请号：US12253783

申请日：2008-10-17

申请人： Robert C. Dixon ,  Robert DeVor ,  Hien M. Le ,  Sarah Lynn Bird

发明人： Robert C. Dixon ,  Robert DeVor ,  Hien M. Le ,  Sarah Lynn Bird

IPC分类号： G01R31/3183 ,  G06F11/263

CPC分类号： G01R31/318511

摘要： A methodology to perform testing of integrated circuits (IC) wherein a reduced number of Input/Output (IO) pins may used to load testing patterns and capture test results from test structures after an IC has been installed in its intended application is provided. This methodology utilizes a software engine that receives and translates a parallel test pattern into serial data patterns operable to be provided on the reduced number of I/O pins. A serial process loader then loads the serial data patterns to the test structures within the IC. The IC receives the serial patterns and in turn translates them into parallel test patterns in order to apply the test patterns to the appropriate test structures. The results are captured and then translated into a serial format for communication from the IC to a test unit for analysis.

摘要翻译： 提供了一种用于执行集成电路（IC）测试的方法，其中减少数量的输入/输出（IO）引脚可用于在将IC安装在其预期应用中之后加载测试模式并从测试结构捕获测试结果。 该方法利用一种软件引擎，该软件引擎将并行测试模式接收并转换为可在减少数量的I / O引脚上提供的串行数据模式。 然后，串行处理加载器将串行数据模式加载到IC内的测试结构。 IC接收串行模式，并将它们转换为并行测试模式，以便将测试模式应用于适当的测试结构。 结果被捕获，然后被转换成用于从IC到用于分析的测试单元的通信的串行格式。

公开(公告)号：US20100235584A1

公开(公告)日：2010-09-16

申请号：US12402025

申请日：2009-03-11

申请人： Guy L. Guthrie ,  Hien M. Le ,  Alvan W. Ng ,  Michael S. Siegel ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  Hien M. Le ,  Alvan W. Ng ,  Michael S. Siegel ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/12 ,  G06F12/128

摘要： A victim cache line having a data-invalid coherence state is selected for castout from a first lower level cache of a first processing unit. The first processing unit issues on an interconnect fabric a lateral castout (LCO) command identifying the victim cache line to be castout from the first lower level cache, indicating the data-invalid coherence state, and indicating that a lower level cache is an intended destination of the victim cache line. In response to a coherence response to the LCO command indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in a second lower level cache of a second processing unit in the data-invalid coherence state.

摘要翻译： 选择具有数据无效相干状态的受害者缓存线，用于从第一处理单元的第一较低级缓存进行舍入。 第一处理单元在互连结构上发出用于标识要从第一较低级高速缓存丢弃的受害缓存行的横向聚合（LCO）命令，指示数据无效相干状态，并指示较低级别高速缓存是预期目的地 的受害者缓存行。 响应于指示LCO命令成功的LCO命令的一致性响应，从第一低级缓存中移除受害者高速缓存行并将其保存在数据无效一致状态中的第二处理单元的第二较低级高速缓存中。

公开(公告)号：US07915884B2

公开(公告)日：2011-03-29

申请号：US12128058

申请日：2008-05-28

申请人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

发明人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

IPC分类号： G01R23/16 ,  G06F17/50

CPC分类号： G01R31/318364 ,  G01R31/318357

摘要： Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

摘要翻译： 通过方法，系统和程序产品促进电子元件验证测试，该产品允许从电子元件设计的模拟验证测试导出的虚拟信号输入到在实际电子元件的验证测试期间使用的电子测试设备。 该方法包括：存储由电子元件设计的仿真测试得到的仿真数据; 采用电子测试设备对实际电子元件进行实时测试，并获得实时测试信号; 将存储的仿真数据与实际的实时测试信号自动相关; 以及使用所述实时测试信号执行将所述相关模拟数据叠加和/或显示为虚拟信号中的至少一个; 并根据所存储的模拟数据自动确定触发事件并触发电子测试设备，从而通过存储的仿真数据自动控制电子部件的实时测试。

公开(公告)号：US07408336B2

公开(公告)日：2008-08-05

申请号：US11259315

申请日：2005-10-26

申请人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

发明人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

IPC分类号： G01R23/16 ,  G06F17/50

CPC分类号： G01R31/318364 ,  G01R31/318357

摘要： Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of: overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

摘要翻译： 通过方法，系统和程序产品促进电子元件验证测试，该产品允许从电子元件设计的模拟验证测试导出的虚拟信号输入到在实际电子元件的验证测试期间使用的电子测试设备。 该方法包括：存储由电子元件设计的仿真测试得到的仿真数据; 采用电子测试设备对实际电子元件进行实时测试，并获得实时测试信号; 将存储的仿真数据与实际的实时测试信号自动相关; 以及执行以下至少之一：用所述实时测试信号叠加和/或显示所述相关仿真数据作为虚拟信号; 并根据所存储的模拟数据自动确定触发事件并触发电子测试设备，从而通过存储的仿真数据自动控制电子部件的实时测试。

公开(公告)号：US20090024346A1

公开(公告)日：2009-01-22

申请号：US12128058

申请日：2008-05-28

申请人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

发明人： Parag Birmiwal ,  Robert C. Dixon ,  Hien M. Le ,  Kirk E. Morrow

IPC分类号： G01R31/00

CPC分类号： G01R31/318364 ,  G01R31/318357

摘要： Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

摘要翻译： 通过方法，系统和程序产品促进电子元件验证测试，该产品允许从电子元件设计的模拟验证测试导出的虚拟信号输入到在实际电子元件的验证测试期间使用的电子测试设备。 该方法包括：存储由电子元件设计的仿真测试得到的仿真数据; 采用电子测试设备对实际电子元件进行实时测试，并获得实时测试信号; 将存储的仿真数据与实际的实时测试信号自动相关; 以及使用所述实时测试信号执行将所述相关模拟数据叠加和/或显示为虚拟信号中的至少一个; 并根据所存储的模拟数据自动确定触发事件并触发电子测试设备，从而通过存储的仿真数据自动控制电子部件的实时测试。