公开(公告)号：US06327194B1

公开(公告)日：2001-12-04

申请号：US09644358

申请日：2000-08-23

申请人： Kazuhiro Kurihara ,  Tien-Min Chen

发明人： Kazuhiro Kurihara ,  Tien-Min Chen

IPC分类号： G11C700

CPC分类号： G11C16/30

摘要： An equalization circuit for the power distribution paths of a high density flash memory device is disclosed. The equalization circuit matches the electrical characteristics of the reference path power distribution to those of the power distribution of the memory array wordlines so as to equalize the resistance and parasitic capacitance to the sense amplifiers.

摘要翻译： 公开了一种用于高密度闪存器件的配电路径的均衡电路。 均衡电路将参考路径功率分布的电特性与存储器阵列字线的功率分布的电特性相匹配，以便使感测放大器的电阻和寄生电容相等。

公开(公告)号：US06272323B1

公开(公告)日：2001-08-07

申请号：US09208134

申请日：1998-12-09

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： H04B140

CPC分类号： H03G3/3068 ,  H03G1/0088 ,  H03G3/3042

摘要： An AGC amplifier control circuit applying for both transmission and reception which the quantity of data memorizing in a memory is decreased and the address of the memory is simplified is provided. The AGC amplifier control circuit provides RF attenuators controlled in hysteresis and these RF attenuators are driven at the next gain renewing time of AGC amplifiers and provides attenuation controllers outputting the information whether the RF attenuators have a fixed attenuation quantity or not. In this construction of circuit, memories memorize the control voltage data of the gain of the AGC amplifiers with the relation of desired outputs, at the time when the RF attenuators are driven and have a fixed attenuation quantity, data conversion circuits convert the data to make the gain of the AGC amplifiers increase corresponding to these attenuation quantities. Therefore, to the address of the memories, by using the value which the transmitting level or the receiving level is converted in consideration of the attenuation quantity of attenuators, the quantity of the data memorizing in the memories are saved in small and the quantity of the data is able to be reduced.

摘要翻译： 提供了一种AGC放大器控制电路，其应用于存储器中存储的数据量减少并且存储器的地址被简化的发送和接收。 AGC放大器控制电路提供在迟滞中控制的RF衰减器，并且这些RF衰减器在AGC放大器的下一个增益更新时间下被驱动，并且提供衰减控制器输出信号，无论RF衰减器是否具有固定的衰减量。 在这种电路结构中，存储器按照期望输出的关系存储AGC放大器的增益的控制电压数据，在RF衰减器被驱动并具有固定的衰减量时，数据转换电路将数据转换成 AGC放大器的增益对应于这些衰减量而增加。 因此，对于存储器的地址，通过使用考虑到衰减器的衰减量来转换发送电平或接收电平的值，保存存储在存储器中的数据量很小，并且数量 数据能够减少。

公开(公告)号：US06272116B1

公开(公告)日：2001-08-07

申请号：US09104372

申请日：1998-06-25

申请人： Kazuhiro Kurihara

发明人： Kazuhiro Kurihara

IPC分类号： H04B726

CPC分类号： H04W52/028 ,  Y02D70/00

摘要： A power saving device of the present invention includes a first demodulation circuit for selectively demodulating modulated signals derived from at least two different systems. A second demodulation circuit demodulates only one of the modulated signals. A detection circuit detects a control signal out of any one of the modulated signals. A controller selects, based on the control signal detected by the detection circuit, either one of the first and second demodulation circuits while deactivating the other demodulation circuit. The device is capable of saving power during receipt of an FM (Frequency Modulation) modulated signal and preventing communication quality from being lowered when signal strength is low.

摘要翻译： 本发明的省电装置包括用于选择性地解调从至少两个不同系统导出的调制信号的第一解调电路。 第二解调电路仅解调调制信号中的一个。 检测电路检测出任一调制信号中的控制信号。 控制器基于检测电路检测到的控制信号，选择第一和第二解调电路中的任一个，同时去激活另一个解调电路。 该装置能够在接收FM（调频）调制信号时节省电力，并且在信号强度低时防止通信质量降低。

公开(公告)号：US06185128B2

公开(公告)日：2001-02-06

申请号：US09421984

申请日：1999-10-19

申请人： Tien-Min Chen ,  Kazuhiro Kurihara ,  Takao Akaogi

发明人： Tien-Min Chen ,  Kazuhiro Kurihara ,  Takao Akaogi

IPC分类号： G11C1604

CPC分类号： G11C16/28 ,  G11C16/3436 ,  G11C2216/22

摘要： A flash memory system capable of simultaneous operation comprises upper and lower memory banks of flash memory cells, reference cells generating reference signals, a switch coupled to the reference cells and upper and lower sense amplifiers coupled to the switch and to the upper and lower memory bank, respectively. The switch steers the appropriate reference signal to the appropriate upper sense amplifier along one upper signal line and steers the appropriate reference signal to the appropriate lower sense amplifier along a lower signal line. The upper and lower sense amplifiers generate comparison signals in response to reference signals and data stored in the upper and lower memory bank, respectively.

摘要翻译： 能够同时操作的闪速存储器系统包括闪存单元的上部和下部存储器组，产生参考信号的参考单元，耦合到参考单元的开关和耦合到该开关的上部和下部读出放大器以及上部和下部存储器组 ， 分别。 开关将适当的参考信号沿着一个上部信号线转向适当的上部读出放大器，并将适当的参考信号沿着较低的信号线转向适当的下部读出放大器。 上和下感测放大器响应于分别存储在上部和下部存储体中的参考信号和数据产生比较信号。

公开(公告)号：US6118698A

公开(公告)日：2000-09-12

申请号：US422199

申请日：1999-10-19

申请人： Takao Akaogi ,  Kazuhiro Kurihara ,  Tien-Min Chen

发明人： Takao Akaogi ,  Kazuhiro Kurihara ,  Tien-Min Chen

IPC分类号： G11C16/26 ,  G11C16/28 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/28

摘要： A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.

摘要翻译： 公开了一种包括用于复用的读出放大器输出信号路径的同步电路的闪存芯片。 同步电路包括信号发生器，读出放大器和输出多路复用器。 来自读出放大器的数据到达输出多路复用器是相等的。 通过调整信号路径长度，从而从信号发生器到读出放大器的信号路径长度的电阻和电容来实现均衡，该读出放大器承载信号以使读出放大器将其数据传输到输出多路复用器。